linux-kernel - Re: [PATCH v2 4/9] drm/msm/A6xx: Implement preemption for A7XX targets

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Message-ID: <CAF6AEGuMah=C_i1qqaAP+Pz5t=bX5+Tq4Mq6HXoSeyWpaj7Cqw@mail.gmail.com>
Date: Fri, 30 Aug 2024 13:36:59 -0700
From: Rob Clark <robdclark@...il.com>
To: Antonino Maniscalco <antomani103@...il.com>
Cc: Sean Paul <sean@...rly.run>, Konrad Dybcio <konrad.dybcio@...aro.org>, 
	Abhinav Kumar <quic_abhinavk@...cinc.com>, Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, 
	Marijn Suijten <marijn.suijten@...ainline.org>, David Airlie <airlied@...il.com>, 
	Daniel Vetter <daniel@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, 
	Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, linux-arm-msm@...r.kernel.org, 
	dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org, 
	linux-kernel@...r.kernel.org, Sharat Masetty <smasetty@...eaurora.org>, 
	Neil Armstrong <neil.armstrong@...aro.org>
Subject: Re: [PATCH v2 4/9] drm/msm/A6xx: Implement preemption for A7XX targets

On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
<antomani103@...il.com> wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from coarse grained(ringbuffer level) to a more fine grained
> such as draw-call level or a bin boundary level preemption. This patch
> enables the basic preemption level, with more fine grained preemption
> support to follow.
>
> Signed-off-by: Sharat Masetty <smasetty@...eaurora.org>
> Signed-off-by: Antonino Maniscalco <antomani103@...il.com>
> Tested-by: Neil Armstrong <neil.armstrong@...aro.org> # on SM8650-QRD
> ---
>  drivers/gpu/drm/msm/Makefile              |   1 +
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c     | 323 +++++++++++++++++++++-
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.h     | 168 ++++++++++++
>  drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 431 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/msm/msm_ringbuffer.h      |   7 +
>  5 files changed, 921 insertions(+), 9 deletions(-)
>

[snip]

> +void a6xx_preempt_trigger(struct msm_gpu *gpu)
> +{
> +       struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> +       struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> +       u64 preempt_offset_priv_secure;
> +       unsigned long flags;
> +       struct msm_ringbuffer *ring;
> +       uint64_t user_ctx_iova;
> +       unsigned int cntl;
> +
> +       if (gpu->nr_rings == 1)
> +               return;
> +
> +       /*
> +        * Lock to make sure another thread attempting preemption doesn't skip it
> +        * while we are still evaluating the next ring. This makes sure the other
> +        * thread does start preemption if we abort it and avoids a soft lock.
> +        */
> +       spin_lock_irqsave(&a6xx_gpu->eval_lock, flags);
> +
> +       /*
> +        * Try to start preemption by moving from NONE to START. If
> +        * unsuccessful, a preemption is already in flight
> +        */
> +       if (!try_preempt_state(a6xx_gpu, PREEMPT_NONE, PREEMPT_START)) {
> +               spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags);
> +               return;
> +       }
> +
> +       cntl = (((a6xx_gpu->preempt_level << 6) & 0xC0) |
> +               ((a6xx_gpu->skip_save_restore << 9) & 0x200) |
> +               ((a6xx_gpu->uses_gmem << 8) & 0x100) | 0x1);

nit, could we define these fields in the xml, and not open-code
register building?

BR,
-R