linux-kernel - Re: [PATCH v3 2/4] clk: qcom: Add CMN PLL clock controller driver for IPQ SoC

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Message-ID: <04944b77ce6327ba5f4ec96348a9cda2.sboyd@kernel.org>
Date: Fri, 30 Aug 2024 15:24:19 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Bjorn Andersson <andersson@...nel.org>, Catalin Marinas <catalin.marinas@....com>, Conor Dooley <conor+dt@...nel.org>, Jie Luo <quic_luoj@...cinc.com>, Konrad Dybcio <konradybcio@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Michael Turquette <mturquette@...libre.com>, Rob Herring <robh@...nel.org>, Will Deacon <will@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, quic_kkumarcs@...cinc.com, quic_suruchia@...cinc.com, quic_pavir@...cinc.com, quic_linchen@...cinc.com, quic_leiwei@...cinc.com, bartosz.golaszewski@...aro.org, srinivas.kandagatla@...aro.org
Subject: Re: [PATCH v3 2/4] clk: qcom: Add CMN PLL clock controller driver for IPQ SoC

Quoting Jie Luo (2024-08-30 09:14:28)
> Hi Stephen,
> Please find below a minor update to my earlier message on clk_ops usage.

Ok. Next time you can trim the reply to save me time.

> On 8/28/2024 1:44 PM, Jie Luo wrote:
> > On 8/28/2024 7:50 AM, Stephen Boyd wrote:
> >> Quoting Luo Jie (2024-08-27 05:46:00)
> >>> +       case 48000000:
> >>> +               val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
> >>> +               break;
> >>> +       case 50000000:
> >>> +               val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8);
> >>> +               break;
> >>> +       case 96000000:
> >>> +               val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
> >>> +               val &= ~CMN_PLL_REFCLK_DIV;
> >>> +               val |= FIELD_PREP(CMN_PLL_REFCLK_DIV, 2);
> >>> +               break;
> >>> +       default:
> >>> +               return -EINVAL;
> >>> +       }
> >>
> >> Why isn't this done with struct clk_ops::set_rate() or clk_ops::init()?
> > 
> > OK, I will move this code into the clk_ops::init().
> 
> This code is expected to be executed once for initializing the CMN PLL
> to enable output clocks, and requires the parent clock rate to be
> available. However the parent clock rate is not available in the
> clk_ops::init(). Hence clk_ops::set_rate() seems to be the right option
> for this. Please let us know if this approach is fine. Thanks.

Sure. It actually sounds like the PLL has a mux to select different
reference clks. Is that right? If so, it seems like there should be
multiple 'clocks' for the DT property and many parents possible. If
that's the case then it should be possible to have something like

	clocks = <0>, <&refclk>, <0>;

in the DT node and then have clk_set_rate() from the consumer actually
set the parent index in hardware. If that's all static then it can be
done with assigned-clock-parents or assigned-clock-rates.