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Message-ID: <20240830075626-GYA41291@gentoo>
Date: Fri, 30 Aug 2024 07:56:26 +0000
From: Yixun Lan <dlan@...too.org>
To: Inochi Amaoto <inochiama@...look.com>
Cc: Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>, Conor Dooley <conor@...nel.org>,
	Yangyu Chen <cyy@...self.name>, Jesse Taube <jesse@...osinc.com>,
	Jisheng Zhang <jszhang@...nel.org>, Icenowy Zheng <uwu@...nowy.me>,
	Meng Zhang <zhangmeng.kevin@...cemit.com>,
	Meng Zhang <kevin.z.m@...mail.com>, devicetree@...r.kernel.org,
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
	linux-gpio@...r.kernel.org
Subject: Re: [PATCH v3 3/4] riscv: dts: spacemit: add pinctrl support for K1
 SoC

Hi

On 09:36 Fri 30 Aug     , Inochi Amaoto wrote:
> On Wed, Aug 28, 2024 at 11:30:25AM GMT, Yixun Lan wrote:
> > Add pinctrl device tree data to SpacemiT's K1 SoC.
> > 
> > Signed-off-by: Yixun Lan <dlan@...too.org>
> > ---
> > Note, only minimal device tree data added in this series,
> > which just try to demonstrate this pinctrl driver, but
> > more dt data can be added later, in separate patches.
> > ---
> >  arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi |  19 ++++
> >  arch/riscv/boot/dts/spacemit/k1-pinctrl.h    | 161 +++++++++++++++++++++++++++
> >  arch/riscv/boot/dts/spacemit/k1.dtsi         |   5 +
> >  3 files changed, 185 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> > new file mode 100644
> > index 0000000000000..1082f92753176
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> > @@ -0,0 +1,19 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (c) 2024 Yixun Lan <dlan@...too.org>
> > + */
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include "k1-pinctrl.h"
> > +
> 
> > +&pinctrl {
> > +	uart0_2_cfg: uart0-2-cfg {
> > +		uart0-2-pins {
> > +			pinmux = <K1_PADCONF(GPIO_68, 2)>,
> > +				 <K1_PADCONF(GPIO_69, 2)>;
> > +
> > +			bias-pull-up = <0>;
> > +			drive-strength = <32>;
> > +		};
> > +	};
> > +};
> 
> "uart0_2"? Is not enough to use "uart0"?
> 
not sure if I understand your point correctly here, are you saying that
we should describe all configurations of the "uart0", as there are indeed
another two options - uart0_0, uart0_1 which using different pins, I can
add them in next version

for uart0_2 itself , I would consider it's a complete configuration

> Although I do not reject to add a new common file, it is better
> for you to squash this part into the next uart dts patch. I think
> this is more related.
> 
I can squash them into one patch but still with separated pinctrl common file,
does this sound good to you?

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

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