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Message-ID: <5gmsbbnuc7sbkpptomvpl6aarw5poutvjfav5rilgogb7727vi@nhtr5m24tkmt>
Date: Fri, 30 Aug 2024 11:13:28 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Danila Tikhonov <danila@...xyga.com>
Cc: andersson@...nel.org, konradybcio@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, cros-qcom-dts-watchers@...omium.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux@...nlining.org
Subject: Re: [PATCH] arm64: dts: qcom: sc7280.dtsi: Fix PMU nodes for Cortex
A55 and A78
On Sun, Aug 18, 2024 at 10:29:05PM GMT, Danila Tikhonov wrote:
> The SC7280, SM7325, and QCM6490 platforms feature an 8-core setup
> consisting of:
> - 1x Kryo 670 Prime (Cortex-A78) / Kryo 670 Gold Plus (Cortex-A78)
> - 3x Kryo 670 Gold (Cortex-A78)
> - 4x Kryo 670 Silver (Cortex-A55)
> (The CPU cores in the SC7280 are simply called Kryo, but are
> nevertheless based on the same Cortex A78 and A55).
>
> Use the correct compatibility.
>
> Signed-off-by: Danila Tikhonov <danila@...xyga.com>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 91cc5e74d8f5..ab024a3c3653 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -845,8 +845,13 @@ wlan_smp2p_in: wlan-wpss-to-ap {
> };
> };
>
> - pmu {
> - compatible = "arm,armv8-pmuv3";
> + pmu-a55 {
> + compatible = "arm,cortex-a55-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + pmu-a78 {
> + compatible = "arm,cortex-a78-pmu";
> interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
Shouldn't these two entries have GIC_CPU_MASK_RAW(), limiting interrupts
to the corresponding cores? I see that in [1] Rob used masks for older
SoCs, but skipped them for newer ones.
[1] https://lore.kernel.org/all/20240417204247.3216703-1-robh@kernel.org/
> };
>
> --
> 2.46.0
>
--
With best wishes
Dmitry
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