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Message-ID:
<IA1PR20MB495369231BB1E1677228D95DBB972@IA1PR20MB4953.namprd20.prod.outlook.com>
Date: Fri, 30 Aug 2024 09:36:38 +0800
From: Inochi Amaoto <inochiama@...look.com>
To: Yixun Lan <dlan@...too.org>, Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Conor Dooley <conor@...nel.org>
Cc: Yangyu Chen <cyy@...self.name>, Jesse Taube <jesse@...osinc.com>,
Jisheng Zhang <jszhang@...nel.org>, Inochi Amaoto <inochiama@...look.com>,
Icenowy Zheng <uwu@...nowy.me>, Meng Zhang <zhangmeng.kevin@...cemit.com>,
Meng Zhang <kevin.z.m@...mail.com>, devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org
Subject: Re: [PATCH v3 3/4] riscv: dts: spacemit: add pinctrl support for K1
SoC
On Wed, Aug 28, 2024 at 11:30:25AM GMT, Yixun Lan wrote:
> Add pinctrl device tree data to SpacemiT's K1 SoC.
>
> Signed-off-by: Yixun Lan <dlan@...too.org>
> ---
> Note, only minimal device tree data added in this series,
> which just try to demonstrate this pinctrl driver, but
> more dt data can be added later, in separate patches.
> ---
> arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 19 ++++
> arch/riscv/boot/dts/spacemit/k1-pinctrl.h | 161 +++++++++++++++++++++++++++
> arch/riscv/boot/dts/spacemit/k1.dtsi | 5 +
> 3 files changed, 185 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> new file mode 100644
> index 0000000000000..1082f92753176
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (c) 2024 Yixun Lan <dlan@...too.org>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include "k1-pinctrl.h"
> +
> +&pinctrl {
> + uart0_2_cfg: uart0-2-cfg {
> + uart0-2-pins {
> + pinmux = <K1_PADCONF(GPIO_68, 2)>,
> + <K1_PADCONF(GPIO_69, 2)>;
> +
> + bias-pull-up = <0>;
> + drive-strength = <32>;
> + };
> + };
> +};
"uart0_2"? Is not enough to use "uart0"?
Although I do not reject to add a new common file, it is better
for you to squash this part into the next uart dts patch. I think
this is more related.
> diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.h b/arch/riscv/boot/dts/spacemit/k1-pinctrl.h
> new file mode 100644
> index 0000000000000..3be4e29553c29
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.h
> @@ -0,0 +1,161 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> +/*
> + * Copyright (c) 2022-2024 SpacemiT (Hangzhou) Technology Co. Ltd
> + * Copyright (c) 2024 Yixun Lan <dlan@...too.org>
> + *
> + */
> +
> +#ifndef _SPACEMIT_K1_PINCTRL_H
> +#define _SPACEMIT_K1_PINCTRL_H
> +
> +#define PINMUX(pin, mux) \
> + (((pin) & 0xffff) | (((mux) & 0xff) << 16))
> +
> +/* pin offset */
> +#define PINID(x) ((x) + 1)
> +
> +#define GPIO_INVAL 0
> +#define GPIO_00 PINID(0)
> +#define GPIO_01 PINID(1)
> +#define GPIO_02 PINID(2)
> +#define GPIO_03 PINID(3)
> +#define GPIO_04 PINID(4)
> +#define GPIO_05 PINID(5)
> +#define GPIO_06 PINID(6)
> +#define GPIO_07 PINID(7)
> +#define GPIO_08 PINID(8)
> +#define GPIO_09 PINID(9)
> +#define GPIO_10 PINID(10)
> +#define GPIO_11 PINID(11)
> +#define GPIO_12 PINID(12)
> +#define GPIO_13 PINID(13)
> +#define GPIO_14 PINID(14)
> +#define GPIO_15 PINID(15)
> +#define GPIO_16 PINID(16)
> +#define GPIO_17 PINID(17)
> +#define GPIO_18 PINID(18)
> +#define GPIO_19 PINID(19)
> +#define GPIO_20 PINID(20)
> +#define GPIO_21 PINID(21)
> +#define GPIO_22 PINID(22)
> +#define GPIO_23 PINID(23)
> +#define GPIO_24 PINID(24)
> +#define GPIO_25 PINID(25)
> +#define GPIO_26 PINID(26)
> +#define GPIO_27 PINID(27)
> +#define GPIO_28 PINID(28)
> +#define GPIO_29 PINID(29)
> +#define GPIO_30 PINID(30)
> +#define GPIO_31 PINID(31)
> +
> +#define GPIO_32 PINID(32)
> +#define GPIO_33 PINID(33)
> +#define GPIO_34 PINID(34)
> +#define GPIO_35 PINID(35)
> +#define GPIO_36 PINID(36)
> +#define GPIO_37 PINID(37)
> +#define GPIO_38 PINID(38)
> +#define GPIO_39 PINID(39)
> +#define GPIO_40 PINID(40)
> +#define GPIO_41 PINID(41)
> +#define GPIO_42 PINID(42)
> +#define GPIO_43 PINID(43)
> +#define GPIO_44 PINID(44)
> +#define GPIO_45 PINID(45)
> +#define GPIO_46 PINID(46)
> +#define GPIO_47 PINID(47)
> +#define GPIO_48 PINID(48)
> +#define GPIO_49 PINID(49)
> +#define GPIO_50 PINID(50)
> +#define GPIO_51 PINID(51)
> +#define GPIO_52 PINID(52)
> +#define GPIO_53 PINID(53)
> +#define GPIO_54 PINID(54)
> +#define GPIO_55 PINID(55)
> +#define GPIO_56 PINID(56)
> +#define GPIO_57 PINID(57)
> +#define GPIO_58 PINID(58)
> +#define GPIO_59 PINID(59)
> +#define GPIO_60 PINID(60)
> +#define GPIO_61 PINID(61)
> +#define GPIO_62 PINID(62)
> +#define GPIO_63 PINID(63)
> +
> +#define GPIO_64 PINID(64)
> +#define GPIO_65 PINID(65)
> +#define GPIO_66 PINID(66)
> +#define GPIO_67 PINID(67)
> +#define GPIO_68 PINID(68)
> +#define GPIO_69 PINID(69)
> +#define GPIO_70 PINID(70)
> +#define GPIO_71 PINID(71)
> +#define GPIO_72 PINID(72)
> +#define GPIO_73 PINID(73)
> +#define GPIO_74 PINID(74)
> +#define GPIO_75 PINID(75)
> +#define GPIO_76 PINID(76)
> +#define GPIO_77 PINID(77)
> +#define GPIO_78 PINID(78)
> +#define GPIO_79 PINID(79)
> +#define GPIO_80 PINID(80)
> +#define GPIO_81 PINID(81)
> +#define GPIO_82 PINID(82)
> +#define GPIO_83 PINID(83)
> +#define GPIO_84 PINID(84)
> +#define GPIO_85 PINID(85)
> +
> +#define GPIO_101 PINID(89)
> +#define GPIO_100 PINID(90)
> +#define GPIO_99 PINID(91)
> +#define GPIO_98 PINID(92)
> +#define GPIO_103 PINID(93)
> +#define GPIO_102 PINID(94)
> +
> +#define GPIO_104 PINID(109)
> +#define GPIO_105 PINID(110)
> +#define GPIO_106 PINID(111)
> +#define GPIO_107 PINID(112)
> +#define GPIO_108 PINID(113)
> +#define GPIO_109 PINID(114)
> +#define GPIO_110 PINID(115)
> +
> +#define GPIO_93 PINID(116)
> +#define GPIO_94 PINID(117)
> +#define GPIO_95 PINID(118)
> +#define GPIO_96 PINID(119)
> +#define GPIO_97 PINID(120)
> +
> +#define GPIO_86 PINID(122)
> +#define GPIO_87 PINID(123)
> +#define GPIO_88 PINID(124)
> +#define GPIO_89 PINID(125)
> +#define GPIO_90 PINID(126)
> +#define GPIO_91 PINID(127)
> +#define GPIO_92 PINID(128)
> +
> +#define GPIO_111 PINID(130)
> +#define GPIO_112 PINID(131)
> +#define GPIO_113 PINID(132)
> +#define GPIO_114 PINID(133)
> +#define GPIO_115 PINID(134)
> +#define GPIO_116 PINID(135)
> +#define GPIO_117 PINID(136)
> +#define GPIO_118 PINID(137)
> +#define GPIO_119 PINID(138)
> +#define GPIO_120 PINID(139)
> +#define GPIO_121 PINID(140)
> +#define GPIO_122 PINID(141)
> +#define GPIO_123 PINID(142)
> +#define GPIO_124 PINID(143)
> +#define GPIO_125 PINID(144)
> +#define GPIO_126 PINID(145)
> +#define GPIO_127 PINID(146)
> +
> +#define SLEW_RATE_SLOW0 0
> +#define SLEW_RATE_SLOW1 1
> +#define SLEW_RATE_MEDIUM 2
> +#define SLEW_RATE_FAST 3
> +
> +#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
> +
> +#endif /* _SPACEMIT_K1_PINCTRL_H */
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index 0777bf9e01183..a2d5f7d4a942a 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -416,6 +416,11 @@ uart9: serial@...17800 {
> status = "disabled";
> };
>
> + pinctrl: pinctrl@...1e000 {
> + compatible = "spacemit,k1-pinctrl";
> + reg = <0x0 0xd401e000 0x0 0x400>;
> + };
> +
> plic: interrupt-controller@...00000 {
> compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> reg = <0x0 0xe0000000 0x0 0x4000000>;
>
> --
> 2.45.2
>
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