linux-kernel - Re: [PATCH v3 1/2] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4

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Message-ID: <ZtG2dUVkdwBpBbix@hovoldconsulting.com>
Date: Fri, 30 Aug 2024 14:09:25 +0200
From: Johan Hovold <johan@...nel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: Abel Vesa <abel.vesa@...aro.org>, Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
	linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, Krzysztof Kozlowski <krzk@...nel.org>,
	Johan Hovold <johan+linaro@...nel.org>
Subject: Re: [PATCH v3 1/2] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy:
 Document the X1E80100 QMP PCIe PHY Gen4 x4

On Fri, Aug 30, 2024 at 01:42:10PM +0300, Dmitry Baryshkov wrote:
> On Fri, Aug 23, 2024 at 10:04:15AM GMT, Abel Vesa wrote:
> > The sixth PCIe instance on X1E80100 can be used in either 4-lane mode or
> > 2-lane mode. Document the 4-lane mode as a separate compatible.
> 
> As the patches were merged, it's too late for this series, but as a
> note: we should think of a way to describe the PHY configuration without
> changing the compatibility strings. The hardware stays the same, it's
> just the number of lanes being wired that changes.

No, this is not about configuration and we need two separate compatibles
as the two PHY instances are distinct and only one of them can be used
in 4-lane mode.

The mistake was to ever describe pcie6a as 2-lane in the x1e80100 dtsi
(and possibly also in the ambiguous commit message above). Whether
pcie6a is used in 4-lane or 2-lane mode is determined by a TCSR
register.

Johan