linux-kernel - Re: [PATCH 3/3] clk: at91: clk-sam9x60-pll: increase maximum amount of plls

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Message-ID: <5853cf17-91a3-4118-ab65-ed8bf2fcf498@tuxon.dev>
Date: Sat, 31 Aug 2024 16:27:18 +0300
From: claudiu beznea <claudiu.beznea@...on.dev>
To: Ryan.Wanner@...rochip.com, mturquette@...libre.com, sboyd@...nel.org,
 nicolas.ferre@...rochip.com, alexandre.belloni@...tlin.com
Cc: linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/3] clk: at91: clk-sam9x60-pll: increase maximum amount
 of plls



On 29.08.2024 19:42, Ryan.Wanner@...rochip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@...rochip.com>
> 
> Increase maximum amount of PLLs to 9 to support SAMA7D65 SoC PLL
> requirements.
> 
> Signed-off-by: Ryan Wanner <Ryan.Wanner@...rochip.com>
> ---
>  drivers/clk/at91/clk-sam9x60-pll.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index fda041102224..cefd9948e103 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -23,7 +23,7 @@
>  #define UPLL_DIV		2
>  #define PLL_MUL_MAX		(FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
>  
> -#define PLL_MAX_ID		7
> +#define PLL_MAX_ID		9

This patch need to go before SAMA7D65 clock driver.

>  
>  struct sam9x60_pll_core {
>  	struct regmap *regmap;