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Message-ID:
 <IA1PR20MB495313BAF0905B4BE5840804BB922@IA1PR20MB4953.namprd20.prod.outlook.com>
Date: Mon, 2 Sep 2024 09:27:26 +0800
From: Inochi Amaoto <inochiama@...look.com>
To: Haylen Chu <heylenay@...look.com>, 
	Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: clock: spacemit: Add clock controlers
 of Spacemit K1 SoC

On Sat, Aug 31, 2024 at 03:47:12PM GMT, Haylen Chu wrote:
> Add definition for the clock controllers of Spacemit K1 SoC. The clock
> tree is managed by several SoC parts, thus different compatible strings
> are added for each.
> 
> Signed-off-by: Haylen Chu <heylenay@...look.com>
> ---
>  .../bindings/clock/spacemit,ccu.yaml          | 116 +++++++++++
>  include/dt-bindings/clock/spacemit,ccu.h      | 197 ++++++++++++++++++
>  2 files changed, 313 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/spacemit,ccu.yaml
>  create mode 100644 include/dt-bindings/clock/spacemit,ccu.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/spacemit,ccu.yaml b/Documentation/devicetree/bindings/clock/spacemit,ccu.yaml
> new file mode 100644
> index 000000000000..90ddfc5e2a2f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/spacemit,ccu.yaml
> @@ -0,0 +1,116 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/spacemit,ccu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Spacemit SoC Clock Controller
> +
> +maintainers:
> +  - Haylen Chu <heylenay@...look.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - spacemit,ccu-apbs
> +      - spacemit,ccu-mpmu
> +      - spacemit,ccu-apbc
> +      - spacemit,ccu-apmu
> +

Add K1 prefix.

> +  clocks: true
> +
> +  clock-names: true
> +
> +  spacemit,mpmu:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      Phandle to the syscon managing "Main PMU (MPMU)" registers
> +
> +  "#clock-cells":
> +    const: 1
> +    description:
> +      See <dt-bindings/clock/spacemit,ccu.h> for valid indices.
> +
> +required:
> +  - compatible
> +  - "#clock-cells"
> +
> +additionalProperties: false
> +


> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: spacemit,ccu-apbs
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 1
> +
> +        clock-names:
> +          const: pll1_2457p6_vco
> +
> +      required:
> +        - compatible
> +        - clocks
> +        - clock-names
> +        - "#clock-cells"
> +        - spacemit,mpmu
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: spacemit,ccu-apbc
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 4
> +
> +        clock-names:
> +          items:
> +            - const: clk_32k
> +            - const: vctcxo_1
> +            - const: vctcxo_24
> +            - const: vctcxo_3
> +
> +      required:
> +        - compatible
> +        - clocks
> +        - clock-names
> +        - "#clock-cells"
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: spacemit,ccu-apmu
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 1
> +
> +        clock-names:
> +          const: vctcxo_24
> +
> +      required:
> +        - compatible
> +        - clocks
> +        - clock-names
> +        - "#clock-cells"
> +

Do not use this weird allOf, split this binding into multiple ones.
This also apply to the binding header if necessary.

> +examples:
> +  - |
> +    syscon_apbs: system-control@...90000 {
> +        compatible = "spacemit,mpmu-syscon", "syscon",
> +        "simple-mfd";

syscon also needs binding.

> +        reg = <0x0 0xd4090000 0x0 0x1000>;
> +
> +        clk_apbs: clock-controller {
> +            compatible = "spacemit,ccu-apbs";
> +            clocks = <&pll1_2457p6_vco>;
> +            clock-names = "pll1_2457p6_vco";
> +            #clock-cells = <1>;
> +            spacemit,mpmu = <&syscon_mpmu>;
> +        };
> +    };
> diff --git a/include/dt-bindings/clock/spacemit,ccu.h b/include/dt-bindings/clock/spacemit,ccu.h
> new file mode 100644
> index 000000000000..ce84690684ff
> --- /dev/null
> +++ b/include/dt-bindings/clock/spacemit,ccu.h
> @@ -0,0 +1,197 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (C) 2024 Haylen Chu <heylenay@...look.com>
> + */
> +
> +#ifndef _DT_BINDINGS_SPACEMIT_CCU_H_
> +#define _DT_BINDINGS_SPACEMIT_CCU_H_
> +
> +/*	APBS clocks	*/
> +#define CLK_PLL2		0
> +#define CLK_PLL3		1
> +#define CLK_PLL1_D2		2
> +#define CLK_PLL1_D3		3
> +#define CLK_PLL1_D4		4
> +#define CLK_PLL1_D5		5
> +#define CLK_PLL1_D6		6
> +#define CLK_PLL1_D7		7
> +#define CLK_PLL1_D8		8
> +#define CLK_PLL1_D11		9
> +#define CLK_PLL1_D13		10
> +#define CLK_PLL1_D23		11
> +#define CLK_PLL1_D64		12
> +#define CLK_PLL1_D10_AUD	13
> +#define CLK_PLL1_D100_AUD	14
> +#define CLK_PLL2_D1		15
> +#define CLK_PLL2_D2		16
> +#define CLK_PLL2_D3		17
> +#define CLK_PLL2_D4		18
> +#define CLK_PLL2_D5		19
> +#define CLK_PLL2_D6		20
> +#define CLK_PLL2_D7		21
> +#define CLK_PLL2_D8		22
> +#define CLK_PLL3_D1		23
> +#define CLK_PLL3_D2		24
> +#define CLK_PLL3_D3		25
> +#define CLK_PLL3_D4		26
> +#define CLK_PLL3_D5		27
> +#define CLK_PLL3_D6		28
> +#define CLK_PLL3_D7		29
> +#define CLK_PLL3_D8		30
> +#define CLK_PLL3_80		31
> +#define CLK_PLL3_40		32
> +#define CLK_PLL3_20		33
> +#define CLK_APBS_NUM		34
> +
> +/*	MPMU clocks	*/
> +#define CLK_PLL1_307P2		0
> +#define CLK_PLL1_76P8		1
> +#define CLK_PLL1_61P44		2
> +#define CLK_PLL1_153P6		3
> +#define CLK_PLL1_102P4		4
> +#define CLK_PLL1_51P2		5
> +#define CLK_PLL1_51P2_AP	6
> +#define CLK_PLL1_57P6		7
> +#define CLK_PLL1_25P6		8
> +#define CLK_PLL1_12P8		9
> +#define CLK_PLL1_12P8_WDT	10
> +#define CLK_PLL1_6P4		11
> +#define CLK_PLL1_3P2		12
> +#define CLK_PLL1_1P6		13
> +#define CLK_PLL1_0P8		14
> +#define CLK_PLL1_351		15
> +#define CLK_PLL1_409P6		16
> +#define CLK_PLL1_204P8		17
> +#define CLK_PLL1_491		18
> +#define CLK_PLL1_245P76		19
> +#define CLK_PLL1_614		20
> +#define CLK_PLL1_47P26		21
> +#define CLK_PLL1_31P5		22
> +#define CLK_PLL1_819		23
> +#define CLK_PLL1_1228		24
> +#define CLK_SLOW_UART		25
> +#define CLK_SLOW_UART1		26
> +#define CLK_SLOW_UART2		27
> +#define CLK_WDT			28
> +#define CLK_RIPC		29
> +#define CLK_I2S_SySCLK		30
> +#define CLK_I2S_BCLK		31
> +#define CLK_APB			32
> +#define CLK_MPMU_NUM		33
> +
> +/*	APBC clocks	*/
> +#define CLK_UART0		0
> +#define CLK_UART2		1
> +#define CLK_UART3		2
> +#define CLK_UART4		3
> +#define CLK_UART5		4
> +#define CLK_UART6		5
> +#define CLK_UART7		6
> +#define CLK_UART8		7
> +#define CLK_UART9		8
> +#define CLK_GPIO		9
> +#define CLK_PWM0		10
> +#define CLK_PWM1		11
> +#define CLK_PWM2		12
> +#define CLK_PWM3		13
> +#define CLK_PWM4		14
> +#define CLK_PWM5		15
> +#define CLK_PWM6		16
> +#define CLK_PWM7		17
> +#define CLK_PWM8		18
> +#define CLK_PWM9		19
> +#define CLK_PWM10		20
> +#define CLK_PWM11		21
> +#define CLK_PWM12		22
> +#define CLK_PWM13		23
> +#define CLK_PWM14		24
> +#define CLK_PWM15		25
> +#define CLK_PWM16		26
> +#define CLK_PWM17		27
> +#define CLK_PWM18		28
> +#define CLK_PWM19		29
> +#define CLK_SSP3		30
> +#define CLK_RTC			31
> +#define CLK_TWSI0		32
> +#define CLK_TWSI1		33
> +#define CLK_TWSI2		34
> +#define CLK_TWSI4		35
> +#define CLK_TWSI5		36
> +#define CLK_TWSI6		37
> +#define CLK_TWSI7		38
> +#define CLK_TWSI8		39
> +#define CLK_TIMERS1		40
> +#define CLK_TIMERS2		41
> +#define CLK_AIB			42
> +#define CLK_ONEWIRE		43
> +#define CLK_SSPA0		44
> +#define CLK_SSPA1		45
> +#define CLK_DRO			46
> +#define CLK_IR			47
> +#define CLK_TSEN		48
> +#define CLK_IPC_AP2AUD		49
> +#define CLK_CAN0		50
> +#define CLK_CAN0_BUS		51
> +#define CLK_APBC_NUM		52
> +
> +/*	APMU clocks	*/
> +#define CLK_CCI550		0
> +#define CLK_CPU_C0_HI		1
> +#define CLK_CPU_C0_CORE		2
> +#define CLK_CPU_C0_ACE		3
> +#define CLK_CPU_C0_TCM		4
> +#define CLK_CPU_C1_HI		5
> +#define CLK_CPU_C1_CORE		6
> +#define CLK_CPU_C1_ACE		7
> +#define CLK_CCIC_4X		8
> +#define CLK_CCIC1PHY		9
> +#define CLK_SDH_AXI		10
> +#define CLK_SDH0		11
> +#define CLK_SDH1		12
> +#define CLK_SDH2		13
> +#define CLK_USB_P1		14
> +#define CLK_USB_AXI		15
> +#define CLK_USB30		16
> +#define CLK_QSPI		17
> +#define CLK_QSPI_BUS		18
> +#define CLK_DMA			19
> +#define CLK_AES			20
> +#define CLK_VPU			21
> +#define CLK_GPU			22
> +#define CLK_EMMC		23
> +#define CLK_EMMC_X		24
> +#define CLK_AUDIO		25
> +#define CLK_HDMI		26
> +#define CLK_PMUA_ACLK		27
> +#define CLK_PCIE0		28
> +#define CLK_PCIE1		29
> +#define CLK_PCIE2		30
> +#define CLK_EMAC0_BUS		31
> +#define CLK_EMAC0_PTP		32
> +#define CLK_EMAC1_BUS		33
> +#define CLK_EMAC1_PTP		34
> +#define CLK_JPG			35
> +#define CLK_JPF_4KAFBC		36
> +#define CLK_JPF_2KAFBC		37
> +#define CLK_CCIC2PHY		38
> +#define CLK_CCIC3PHY		39
> +#define CLK_CSI			40
> +#define CLK_CAMM0		41
> +#define CLK_CAMM1		42
> +#define CLK_CAMM2		43
> +#define CLK_ISP_CPP		44
> +#define CLK_ISP_BUS		45
> +#define CLK_ISP			46
> +#define CLK_DPU_MCL		47
> +#define CLK_DPU_ESC		48
> +#define CLK_DPU_BIT		49
> +#define CLK_DPU_PXCLK		50
> +#define CLK_DPU_HCLK		51
> +#define CLK_DPU_SPI		52
> +#define CLK_DPU_SPI_HBUS	53
> +#define CLK_DPU_SPIBUS		54
> +#define CLK_DPU_SPI_ACLK	55
> +#define CLK_V2D			56
> +#define CLK_APMU_NUM		57
> +
> +#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */
> -- 
> 2.46.0
> 

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