linux-kernel - Re: [PATCH] clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883

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Message-ID: <CAMhs-H_NS-n2tx5SZpCMiVZtBFzX_nTa_vnS8We0UevkwFq93Q@mail.gmail.com>
Date: Mon, 2 Sep 2024 11:49:45 +0200
From: Sergio Paracuellos <sergio.paracuellos@...il.com>
To: linux-clk@...r.kernel.org
Cc: mturquette@...libre.com, sboyd@...nel.org, tsbogend@...ha.franken.de, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883

Hi Stephen,

On Tue, Aug 6, 2024 at 4:29 PM Sergio Paracuellos
<sergio.paracuellos@...il.com> wrote:
>
> Clock plan for Ralink SoC RT3883 needs an extra 'periph' clock to properly
> set some peripherals that has this clock as their parent. When this driver
> was mainlined we could not find any active users of this SoC so we cannot
> perform any real tests for it. Now, one user of a Belkin f9k1109 version 1
> device which uses this SoC appear and reported some issues in openWRT:
> - https://github.com/openwrt/openwrt/issues/16054
> The peripherals that are wrong are 'uart', 'i2c', 'i2s' and 'uartlite' which
> has a not defined 'periph' clock as parent. Hence, introduce it to have a
> properly working clock plan for this SoC.
>
> Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@...il.com>
> ---
>  drivers/clk/ralink/clk-mtmips.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/ralink/clk-mtmips.c b/drivers/clk/ralink/clk-mtmips.c
> index 50a443bf79ec..787ff3e66b34 100644
> --- a/drivers/clk/ralink/clk-mtmips.c
> +++ b/drivers/clk/ralink/clk-mtmips.c
> @@ -267,6 +267,11 @@ static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {
>         CLK_FIXED("xtal", NULL, 40000000)
>  };
>
> +static struct mtmips_clk_fixed rt3383_fixed_clocks[] = {
> +       CLK_FIXED("xtal", NULL, 40000000),
> +       CLK_FIXED("periph", "xtal", 40000000)
> +};
> +
>  static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
>         CLK_FIXED("periph", "xtal", 40000000)
>  };
> @@ -779,8 +784,8 @@ static const struct mtmips_clk_data rt3352_clk_data = {
>  static const struct mtmips_clk_data rt3883_clk_data = {
>         .clk_base = rt3883_clks_base,
>         .num_clk_base = ARRAY_SIZE(rt3883_clks_base),
> -       .clk_fixed = rt305x_fixed_clocks,
> -       .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
> +       .clk_fixed = rt3383_fixed_clocks,
> +       .num_clk_fixed = ARRAY_SIZE(rt3383_fixed_clocks),
>         .clk_factor = NULL,
>         .num_clk_factor = 0,
>         .clk_periph = rt5350_pherip_clks,
> --
> 2.25.1
>

Gentle ping on this patch :)

Thanks,
    Sergio Paracuellos