linux-kernel - Re: [PATCH v6 07/13] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU

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Message-ID: <2f3e01d0-9b4b-4678-b05b-226074579b8a@broadcom.com>
Date: Tue, 3 Sep 2024 10:45:41 -0700
From: Florian Fainelli <florian.fainelli@...adcom.com>
To: Bjorn Helgaas <helgaas@...nel.org>,
 Jim Quinlan <james.quinlan@...adcom.com>
Cc: linux-pci@...r.kernel.org, Nicolas Saenz Julienne <nsaenz@...nel.org>,
 Bjorn Helgaas <bhelgaas@...gle.com>,
 Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
 Cyril Brulebois <kibi@...ian.org>, Stanimir Varbanov <svarbanov@...e.de>,
 Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
 Krzysztof Kozlowski <krzk@...nel.org>,
 bcm-kernel-feedback-list@...adcom.com, jim2101024@...il.com,
 Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Krzysztof Wilczyński <kw@...ux.com>,
 Rob Herring <robh@...nel.org>,
 "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
 <linux-rpi-kernel@...ts.infradead.org>,
 "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
 <linux-arm-kernel@...ts.infradead.org>,
 open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v6 07/13] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG,
 INTR2_CPU_BASE offsets SoC-specific

On 9/2/24 12:46, Bjorn Helgaas wrote:
> On Thu, Aug 15, 2024 at 06:57:20PM -0400, Jim Quinlan wrote:
>> Do prepatory work for the 7712 SoC, which is introduced in a future commit.
>> Our HW design has changed two register offsets for the 7712, where
>> previously it was a common value for all Broadcom SOCs with PCIe cores.
>> Specifically, the two offsets are to the registers HARD_DEBUG and
>> INTR2_CPU_BASE.
> 
>> @@ -1499,12 +1502,16 @@ static const int pcie_offsets[] = {
>>   	[RGR1_SW_INIT_1] = 0x9210,
>>   	[EXT_CFG_INDEX]  = 0x9000,
>>   	[EXT_CFG_DATA]   = 0x9004,
>> +	[PCIE_HARD_DEBUG] = 0x4204,
>> +	[PCIE_INTR2_CPU_BASE] = 0x4300,
>>   };
>>   
>>   static const int pcie_offsets_bmips_7425[] = {
>>   	[RGR1_SW_INIT_1] = 0x8010,
>>   	[EXT_CFG_INDEX]  = 0x8300,
>>   	[EXT_CFG_DATA]   = 0x8304,
>> +	[PCIE_HARD_DEBUG] = 0x4204,
>> +	[PCIE_INTR2_CPU_BASE] = 0x4300,
>>   };
>>   
>>   static const struct pcie_cfg_data generic_cfg = {
>> @@ -1539,6 +1546,8 @@ static const int pcie_offset_bcm7278[] = {
>>   	[RGR1_SW_INIT_1] = 0xc010,
>>   	[EXT_CFG_INDEX] = 0x9000,
>>   	[EXT_CFG_DATA] = 0x9004,
>> +	[PCIE_HARD_DEBUG] = 0x4204,
>> +	[PCIE_INTR2_CPU_BASE] = 0x4300,
>>   };
> 
> What's the organization scheme here?  We now have:
> 
>    static const int pcie_offsets[] = { ... };
>    static const int pcie_offsets_bmips_7425[] = { ... };
>    static const int pcie_offset_bcm7712[] = { ... };
> 
>    static const struct pcie_cfg_data generic_cfg = { ... };
>    static const struct pcie_cfg_data bcm7425_cfg = { ... };
>    static const struct pcie_cfg_data bcm7435_cfg = { ... };
>    static const struct pcie_cfg_data bcm4908_cfg = { ... };
> 
>    static const int pcie_offset_bcm7278[] = { ... };
> 
>    static const struct pcie_cfg_data bcm7278_cfg = { ... };
>    static const struct pcie_cfg_data bcm2711_cfg = { ... };
>    static const struct pcie_cfg_data bcm7216_cfg = { ... };
>    static const struct pcie_cfg_data bcm7712_cfg = { ... };
> 
> So we have pcie_offsets_bmips_7425[] and pcie_offset_bcm7712[] (with
> gratuituously different "offset" vs "offsets") which are all together
> before the pcie_cfg_data.
> 
> Then we have pcie_offset_bcm7278[] (again gratuitously different
> "offset") separately, next to bcm7278_cfg.
> 
> It would be nice to pick one scheme and stick to it.
> 
> Also a seemingly random order of the pcie_cfg_data structs and
> .compatible strings.
> 
> Also a little confusing to have "bmips_7425" and "bcm7425" associated
> with the same chip.  I suppose there's historical reason for it, but I
> don't think it's helpful in this usage.

All fair points, especially the lack of consistency, thanks for cleaning 
that up.
-- 
Florian