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Message-ID: <CAPLW+4ns=6eO=S4Cz70aBSyVO8CJ5=ixmKL38dZDjD3UgO98ZA@mail.gmail.com>
Date: Tue, 3 Sep 2024 16:20:04 -0500
From: Sam Protsenko <semen.protsenko@...aro.org>
To: Ivaylo Ivanov <ivo.ivanov.ivanov1@...il.com>
Cc: Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Alim Akhtar <alim.akhtar@...sung.com>, Sylwester Nawrocki <s.nawrocki@...sung.com>,
Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh+dt@...nel.org>,
linux-samsung-soc@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 05/10] pinctrl: samsung: Add exynos8895 SoC pinctrl configuration
On Tue, Sep 3, 2024 at 7:46 AM Ivaylo Ivanov
<ivo.ivanov.ivanov1@...il.com> wrote:
>
> Add support for the pin-controller found on the Exynos8895 SoC
> used in Samsung Galaxy S8 and S8 Plus phones.
>
> It has a newly applied pinctrl register layer for FSYS0 with a
> different bank type offset that consists of the following bit
> fields:
>
> CON: 4, DAT: 1, PUD: 2, DRV: 3, CONPDN: 2, PUDPDN: 2
>
> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@...il.com>
> ---
Other than minor comments below, LGTM:
Reviewed-by: Sam Protsenko <semen.protsenko@...aro.org>
> .../pinctrl/samsung/pinctrl-exynos-arm64.c | 137 ++++++++++++++++++
> drivers/pinctrl/samsung/pinctrl-exynos.h | 10 ++
> drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
> drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
> 4 files changed, 150 insertions(+)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index 5480e0884..0d5d14cf0 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> @@ -58,6 +58,15 @@ static const struct samsung_pin_bank_type exynos850_bank_type_alive = {
> .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
> };
>
> +/*
> + * Bank type for non-alive type. Bit fields:
> + * CON: 4, DAT: 1, PUD: 2, DRV: 3, CONPDN: 2, PUDPDN: 2
> + */
> +static const struct samsung_pin_bank_type exynos8895_bank_type_off = {
> + .fld_width = { 4, 1, 2, 3, 2, 2, },
> + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
> +};
> +
> /* Pad retention control code for accessing PMU regmap */
> static atomic_t exynos_shared_retention_refcnt;
>
> @@ -866,6 +875,134 @@ const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst =
> .num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl),
> };
>
> +/* pin banks of exynos8895 pin-controller 0 (ALIVE) */
> +static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = {
> + EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00),
> + EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04),
> + EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08),
> + EXYNOS_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c),
> + EXYNOS_PIN_BANK_EINTW(7, 0x0A0, "gpa4", 0x24),
> +};
> +
> +/* pin banks of exynos8895 pin-controller 1 (ABOX) */
> +static const struct samsung_pin_bank_data exynos8895_pin_banks1[] __initconst = {
> + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00),
> + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gph1", 0x04),
> + EXYNOS_PIN_BANK_EINTG(4, 0x040, "gph3", 0x08),
> +};
> +
> +/* pin banks of exynos8895 pin-controller 2 (VTS) */
> +static const struct samsung_pin_bank_data exynos8895_pin_banks2[] __initconst = {
> + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gph2", 0x00),
> +};
> +
> +/* pin banks of exynos8895 pin-controller 3 (FSYS0) */
> +static const struct samsung_pin_bank_data exynos8895_pin_banks3[] __initconst = {
> + EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpi0", 0x00),
> + EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi1", 0x04),
> +};
> +
> +/* pin banks of exynos8895 pin-controller 4 (FSYS1) */
> +static const struct samsung_pin_bank_data exynos8895_pin_banks4[] __initconst = {
> + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj1", 0x00),
> + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpj0", 0x04),
> +};
> +
> +/* pin banks of exynos8895 pin-controller 5 (BUSC) */
> +static const struct samsung_pin_bank_data exynos8895_pin_banks5[] __initconst = {
> + EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpb2", 0x00),
> +};
> +
> +/* pin banks of exynos8895 pin-controller 6 (PERIC0) */
> +static const struct samsung_pin_bank_data exynos8895_pin_banks6[] __initconst = {
> + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpd0", 0x00),
> + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpd1", 0x04),
> + EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpd2", 0x08),
> + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpd3", 0x0C),
Here and below: please use lower-case letters for hex values. So 0x0C
-> 0x0c, etc.
> + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
> + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpe7", 0x14),
> + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpf1", 0x18),
> +};
> +
> +/* pin banks of exynos8895 pin-controller 7 (PERIC1) */
> +static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst = {
> + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpb0", 0x00),
> + EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpc0", 0x04),
> + EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpc1", 0x08),
> + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpc2", 0x0C),
> + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
> + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpk0", 0x14),
> + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpe5", 0x18),
> + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe6", 0x1C),
> + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe2", 0x20),
> + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpe3", 0x24),
> + EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe4", 0x28),
> + EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpf0", 0x2C),
> + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe1", 0x30),
> + EXYNOS_PIN_BANK_EINTG(2, 0x1A0, "gpg0", 0x34),
> +};
> +
> +static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = {
> + {
> + /* pin-controller instance 0 Alive data */
Wouldn't it be better to capitalize it, i.e. Alive -> ALIVE?
> + .pin_banks = exynos8895_pin_banks0,
> + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks0),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .eint_wkup_init = exynos_eint_wkup_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin-controller instance 1 ABOX data */
> + .pin_banks = exynos8895_pin_banks1,
> + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks1),
> + }, {
> + /* pin-controller instance 2 VTS data */
> + .pin_banks = exynos8895_pin_banks2,
> + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks2),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + }, {
> + /* pin-controller instance 3 FSYS0 data */
> + .pin_banks = exynos8895_pin_banks3,
> + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks3),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin-controller instance 4 FSYS1 data */
> + .pin_banks = exynos8895_pin_banks4,
> + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks4),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin-controller instance 5 BUSC data */
> + .pin_banks = exynos8895_pin_banks5,
> + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks5),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin-controller instance 6 PERIC0 data */
> + .pin_banks = exynos8895_pin_banks6,
> + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks6),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin-controller instance 7 PERIC1 data */
> + .pin_banks = exynos8895_pin_banks7,
> + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks7),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + },
> +};
> +
> +const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = {
> + .ctrl = exynos8895_pin_ctrl,
> + .num_ctrl = ARRAY_SIZE(exynos8895_pin_ctrl),
> +};
> +
> /*
> * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
> * gpio/pin-mux/pinconfig controllers.
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> index 305cb1d31..7b7ff7ffe 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> @@ -141,6 +141,16 @@
> .name = id \
> }
>
> +#define EXYNOS8895_PIN_BANK_EINTG(pins, reg, id, offs) \
> + { \
> + .type = &exynos8895_bank_type_off, \
> + .pctl_offset = reg, \
> + .nr_pins = pins, \
> + .eint_type = EINT_TYPE_GPIO, \
> + .eint_offset = offs, \
> + .name = id \
> + }
> +
> #define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \
> { \
> .type = &exynos850_bank_type_off, \
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> index 623df65a5..ea3214897 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> @@ -1409,6 +1409,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
> .data = &exynos7885_of_data },
> { .compatible = "samsung,exynos850-pinctrl",
> .data = &exynos850_of_data },
> + { .compatible = "samsung,exynos8895-pinctrl",
> + .data = &exynos8895_of_data },
> { .compatible = "samsung,exynosautov9-pinctrl",
> .data = &exynosautov9_of_data },
> { .compatible = "samsung,exynosautov920-pinctrl",
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> index d50ba6f07..f18877f2f 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> @@ -363,6 +363,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
> extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
> extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
> extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
> +extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
> extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
> extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;
> extern const struct samsung_pinctrl_of_match_data fsd_of_data;
> --
> 2.34.1
>
>
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