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Message-ID: <CACD3sJass-6gu6MQxrYwLGi6OMgWnntO+N7Ob9nV6o3siFHNVg@mail.gmail.com>
Date: Tue, 3 Sep 2024 10:07:45 +0800
From: Tyrone Ting <warp5tw@...il.com>
To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>, avifishman70@...il.com, 
	tmaimon77@...il.com, tali.perry1@...il.com, venture@...gle.com, 
	yuenn@...gle.com, benjaminfair@...gle.com, andi.shyti@...nel.org, 
	wsa@...nel.org, rand.sec96@...il.com, wsa+renesas@...g-engineering.com, 
	kwliu@...oton.com, jjliu0@...oton.com, avi.fishman@...oton.com, 
	tali.perry@...oton.com, tomer.maimon@...oton.com, kfting@...oton.com
Cc: openbmc@...ts.ozlabs.org, linux-i2c@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 5/7] i2c: npcm: Modify the client address assignment

Hi Andy:

Thank you for your feedback.

Andy Shevchenko <andriy.shevchenko@...ux.intel.com> 於 2024年9月2日 週一 下午7:54寫道:
>
> On Mon, Sep 02, 2024 at 09:40:09AM +0800, Tyrone Ting wrote:
> > Andy Shevchenko <andriy.shevchenko@...ux.intel.com> 於 2024年8月31日 週六 上午3:16寫道:
> > > On Fri, Aug 30, 2024 at 11:46:38AM +0800, Tyrone Ting wrote:
> > > > Store the client address earlier since it's used in the i2c_recover_bus
> > > > logic flow.
> > >
> > > Here no explanation why it's now left-shifted by one bit.
> >
> > The address is stored from bit 1 to bit 7 in the register for sending
> > the i2c address later.
>
> Yes, but previously it was stored w/o that shift.
>

Previously, the address was stored w/o that shift and with that shift
in the following call to npcm_i2c_master_start_xmit,
just like what https://github.com/torvalds/linux/blob/master/drivers/i2c/busses/i2c-npcm7xx.c#L2043
shows.

Since there are cases that the i2c_recover_bus gets called at the
early stage of the function npcm_i2c_master_xfer,
the address is stored with the shift and used in the i2c_recover_bus call.

> > I'll write some comments about the left-shifted by one bit behavior
> > above this modification in next patch set.
>
> --
> With Best Regards,
> Andy Shevchenko
>
>

Thank you.

Regards,
Tyrone

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