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Message-ID: <CAPDyKFroWmE+P8S5XD5b2BgnnPjNO3B1XpOHsZAGU8rUOsEarQ@mail.gmail.com>
Date: Tue, 3 Sep 2024 14:37:28 +0200
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Dharma Balasubiramani <dharma.b@...rochip.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Nicolas Ferre <nicolas.ferre@...rochip.com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>, Claudiu Beznea <claudiu.beznea@...on.dev>,
Aubin Constans <aubin.constans@...rochip.com>, linux-mmc@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4] dt-bindings: mmc: sdhci-atmel: Convert to json schema
On Mon, 2 Sept 2024 at 12:57, Dharma Balasubiramani
<dharma.b@...rochip.com> wrote:
>
> Convert sdhci-atmel documentation to yaml format. The new file will inherit
> from sdhci-common.yaml.
>
> Note: Add microchip,sama7g5-sdhci to compatible list as we already use it
> in the DT.
>
> Signed-off-by: Dharma Balasubiramani <dharma.b@...rochip.com>
Applied for next, thanks!
Kind regards
Uffe
> ---
> This patch series converts the sdhci-atmel dt-binding to yaml format and adds
> the sama7d65,sama7g5 compatibles to the list.
> ---
> Changes in v4:
> - remove the "atmel,sama5d3-sdhci" and "atmel,sama5d4-sdhci" compatibles and
> add back the "microchip,sam9x7-sdhci" compatible from old binding which was missed.
> - drop the addition of sama7d65 in binding, will be sent along with the dts patch series.
> - Add the entire description of "microchip,sdcal-inverted" from old txt binding.
> - The microchip,sam9x7-sdhci is yet to be merged in DTS
> https://lore.kernel.org/lkml/20240729070934.1991467-1-varshini.rajendran@microchip.com/
> - Link to v3: https://lore.kernel.org/r/20240830-atmel-sdhci-v3-0-7c97a0872af4@microchip.com
>
> Changes in v3:
> - update the items in clocks instead of plain description.
> - move the items list to clock-names.
> - since baseclk is must, change maxitems to minitems: 3, and modify the
> conditional bits accordingly.
> - Link to v2: https://lore.kernel.org/r/20240830-atmel-sdhci-v2-0-b7f58973f3fc@microchip.com
>
> Changes in v2:
> - Add missing deleted file to the patch
> "Documentation/devicetree/bindings/mmc/sdhci-atmel.txt"
> - Link to v1: https://lore.kernel.org/r/20240830-atmel-sdhci-v1-0-01e3ec8c9804@microchip.com
> ---
> .../bindings/mmc/atmel,sama5d2-sdhci.yaml | 92 ++++++++++++++++++++++
> .../devicetree/bindings/mmc/sdhci-atmel.txt | 35 --------
> 2 files changed, 92 insertions(+), 35 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml b/Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml
> new file mode 100644
> index 000000000000..8c8ade88e8fe
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml
> @@ -0,0 +1,92 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mmc/atmel,sama5d2-sdhci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Atmel SDHCI controller
> +
> +maintainers:
> + - Aubin Constans <aubin.constans@...rochip.com>
> + - Nicolas Ferre <nicolas.ferre@...rochip.com>
> +
> +description:
> + Bindings for the SDHCI controller found in Atmel/Microchip SoCs.
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - atmel,sama5d2-sdhci
> + - microchip,sam9x60-sdhci
> + - items:
> + - enum:
> + - microchip,sam9x7-sdhci
> + - microchip,sama7g5-sdhci
> + - const: microchip,sam9x60-sdhci
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: hclock
> + - description: multclk
> + - description: baseclk
> + minItems: 2
> +
> + clock-names:
> + items:
> + - const: hclock
> + - const: multclk
> + - const: baseclk
> + minItems: 2
> +
> + microchip,sdcal-inverted:
> + type: boolean
> + description:
> + When present, polarity on the SDCAL SoC pin is inverted. The default
> + polarity for this signal is described in the datasheet. For instance on
> + SAMA5D2, the pin is usually tied to the GND with a resistor and a
> + capacitor (see "SDMMC I/O Calibration" chapter).
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +allOf:
> + - $ref: sdhci-common.yaml#
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - atmel,sama5d2-sdhci
> + then:
> + properties:
> + clocks:
> + minItems: 3
> + clock-names:
> + minItems: 3
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/at91.h>
> + mmc@...00000 {
> + compatible = "atmel,sama5d2-sdhci";
> + reg = <0xa0000000 0x300>;
> + interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
> + clock-names = "hclock", "multclk", "baseclk";
> + assigned-clocks = <&sdmmc0_gclk>;
> + assigned-clock-rates = <480000000>;
> + };
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt b/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt
> deleted file mode 100644
> index a9fb0a91245f..000000000000
> --- a/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt
> +++ /dev/null
> @@ -1,35 +0,0 @@
> -* Atmel SDHCI controller
> -
> -This file documents the differences between the core properties in
> -Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the
> -sdhci-of-at91 driver.
> -
> -Required properties:
> -- compatible: Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci"
> - or "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci".
> -- clocks: Phandlers to the clocks.
> -- clock-names: Must be "hclock", "multclk", "baseclk" for
> - "atmel,sama5d2-sdhci".
> - Must be "hclock", "multclk" for "microchip,sam9x60-sdhci".
> - Must be "hclock", "multclk" for "microchip,sam9x7-sdhci".
> -
> -Optional properties:
> -- assigned-clocks: The same with "multclk".
> -- assigned-clock-rates The rate of "multclk" in order to not rely on the
> - gck configuration set by previous components.
> -- microchip,sdcal-inverted: when present, polarity on the SDCAL SoC pin is
> - inverted. The default polarity for this signal is described in the datasheet.
> - For instance on SAMA5D2, the pin is usually tied to the GND with a resistor
> - and a capacitor (see "SDMMC I/O Calibration" chapter).
> -
> -Example:
> -
> -mmc0: sdio-host@...00000 {
> - compatible = "atmel,sama5d2-sdhci";
> - reg = <0xa0000000 0x300>;
> - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
> - clock-names = "hclock", "multclk", "baseclk";
> - assigned-clocks = <&sdmmc0_gclk>;
> - assigned-clock-rates = <480000000>;
> -};
>
> ---
> base-commit: 4b7d983dd85a5cdf4938f4a0a93adedf697ac04d
> change-id: 20240830-atmel-sdhci-c9a92b710624
>
> Best regards,
> --
> Dharma Balasubiramani <dharma.b@...rochip.com>
>
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