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Message-ID: <20240904143734.GA3032973@rocinante>
Date: Wed, 4 Sep 2024 23:37:34 +0900
From: Krzysztof WilczyƄski <kw@...ux.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: Xiaowei Song <songxiaowei@...ilicon.com>,
	Binghui Wang <wangbinghui@...ilicon.com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Marek Vasut <marek.vasut+renesas@...il.com>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
	Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>,
	Masami Hiramatsu <mhiramat@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>, linux-pci@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 1/3] dt-bindings: PCI: hisilicon,kirin-pcie: add
 top-level constraints

Hello,

> Properties with variable number of items per each device are expected to
> have widest constraints in top-level "properties:" block and further
> customized (narrowed) in "if:then:".  Add missing top-level constraints
> for clock-names and reset-names.

Applied to dt-bindings, thank you!

[01/03] dt-bindings: PCI: hisilicon,kirin-pcie: Add top-level constraints
        https://git.kernel.org/pci/pci/c/ac44be2155cd

[02/03] dt-bindings: PCI: renesas,pci-rcar-gen2: Add top-level constraints
        https://git.kernel.org/pci/pci/c/c62a0b8fe8bf

[03/03] dt-bindings: PCI: socionext,uniphier-pcie-ep: Add top-level constraints
        https://git.kernel.org/pci/pci/c/a5c1bf7e9a46

	Krzysztof

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