linux-kernel - Re: [PATCH 18/19] arm64: dts: qcom: add initial support for QCS8300 DTSI

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <be8b573c-db4e-4eec-a9a6-3cd83d04156d@kernel.org>
Date: Wed, 4 Sep 2024 11:41:56 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Jingyi Wang <quic_jingyw@...cinc.com>,
 Bjorn Andersson <andersson@...nel.org>,
 Mathieu Poirier <mathieu.poirier@...aro.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Bartosz Golaszewski <bartosz.golaszewski@...aro.org>,
 Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
 Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
 Alim Akhtar <alim.akhtar@...sung.com>, Avri Altman <avri.altman@....com>,
 Bart Van Assche <bvanassche@....org>, Andy Gross <agross@...nel.org>,
 Ulf Hansson <ulf.hansson@...aro.org>, Thomas Gleixner <tglx@...utronix.de>,
 Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
 Joerg Roedel <joro@...tes.org>, Konrad Dybcio <konradybcio@...nel.org>,
 Robert Marko <robimarko@...il.com>, Das Srinagesh <quic_gurus@...cinc.com>,
 Jassi Brar <jassisinghbrar@...il.com>, Lee Jones <lee@...nel.org>,
 Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
 Catalin Marinas <catalin.marinas@....com>
Cc: linux-arm-msm@...r.kernel.org, linux-remoteproc@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-phy@...ts.infradead.org, linux-scsi@...r.kernel.org,
 linux-pm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 iommu@...ts.linux.dev, Zhenhua Huang <quic_zhenhuah@...cinc.com>,
 Xin Liu <quic_liuxin@...cinc.com>, Kyle Deng <quic_chunkaid@...cinc.com>,
 Tingguo Cheng <quic_tingguoc@...cinc.com>,
 Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
Subject: Re: [PATCH 18/19] arm64: dts: qcom: add initial support for QCS8300
 DTSI

On 04/09/2024 10:33, Jingyi Wang wrote:
> Add initial DTSI for QCS8300 SoC.
> 
> This revision brings support for:
> - CPUs with cpu idle
> - interrupt-controller with PDC wakeup support
> - gcc
> - TLMM
> - interconnect
> - qup with uart
> - smmu
> - pmic
> - ufs
> - ipcc
> - sram
> - remoteprocs including ADSP,CDSP and GPDSP
> 
> [Zhenhua: added the smmu node]
> Co-developed-by: Zhenhua Huang <quic_zhenhuah@...cinc.com>
> Signed-off-by: Zhenhua Huang <quic_zhenhuah@...cinc.com>
> [Xin: added ufs/adsp/gpdsp nodes]
> Co-developed-by: Xin Liu <quic_liuxin@...cinc.com>
> Signed-off-by: Xin Liu <quic_liuxin@...cinc.com>
> [Kyle: added the aoss_qmp node]
> Co-developed-by: Kyle Deng <quic_chunkaid@...cinc.com>
> Signed-off-by: Kyle Deng <quic_chunkaid@...cinc.com>
> [Tingguo: added the pmic nodes]
> Co-developed-by: Tingguo Cheng <quic_tingguoc@...cinc.com>
> Signed-off-by: Tingguo Cheng <quic_tingguoc@...cinc.com>
> [Raviteja: added interconnect nodes]
> Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
> Signed-off-by: Jingyi Wang <quic_jingyw@...cinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs8300.dtsi | 1282 +++++++++++++++++++++++++++++++++
>  1 file changed, 1282 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> new file mode 100644
> index 000000000000..244fa8bf97d9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -0,0 +1,1282 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/power/qcom,rpmhpd.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	clocks {
> +		sleep_clk: sleep-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <32000>;

Are you sure that sleep clock is physically part of the SoC?

> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +

...

> +
> +	soc: soc@0 {
> +		compatible = "simple-bus";
> +
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges = <0 0 0 0 0x10 0>;

ranges follow compatible, so it is the second property.



Best regards,
Krzysztof