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Message-ID: <ZtguJs128O-N07Eg@hovoldconsulting.com>
Date: Wed, 4 Sep 2024 11:53:42 +0200
From: Johan Hovold <johan@...nel.org>
To: manivannan.sadhasivam@...aro.org
Cc: Richard Zhu <hongxing.zhu@....com>,
Lucas Stach <l.stach@...gutronix.de>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
Jingoo Han <jingoohan1@...il.com>,
Chuanhua Lei <lchuanhua@...linear.com>,
Marek Vasut <marek.vasut+renesas@...il.com>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
imx@...ts.linux.dev, linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, linux-arm-msm@...r.kernel.org,
abel.vesa@...aro.org, johan+linaro@...nel.org,
Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>
Subject: Re: [PATCH v6 4/4] PCI: qcom: Add RX margining settings for 16.0 GT/s
On Wed, Sep 04, 2024 at 12:42:00PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> From: Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>
>
> Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate. These
> settings improve link stability while operating at high date rates and
> helps to improve signal quality.
>
> Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> [mani: dropped the code refactoring and minor changes]
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---
> drivers/pci/controller/dwc/pcie-designware.h | 18 ++++++++++++++++
> drivers/pci/controller/dwc/pcie-qcom-common.c | 31 +++++++++++++++++++++++++++
> drivers/pci/controller/dwc/pcie-qcom-common.h | 1 +
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +++-
> drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
> 5 files changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 51744ad25575..f5be99731f7e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -209,6 +209,24 @@
>
> #define PCIE_PL_CHK_REG_ERR_ADDR 0xB28
>
> +/*
> + * 16.0 GT/s (GEN4) lane margining register definitions
nit: Gen 4?
> + */
> +#define GEN4_LANE_MARGINING_1_OFF 0xb80
nit: upper case hex
> +#define MARGINING_MAX_VOLTAGE_OFFSET GENMASK(29, 24)
> +#define MARGINING_NUM_VOLTAGE_STEPS GENMASK(22, 16)
> +#define MARGINING_MAX_TIMING_OFFSET GENMASK(13, 8)
> +#define MARGINING_NUM_TIMING_STEPS GENMASK(5, 0)
> +
> +#define GEN4_LANE_MARGINING_2_OFF 0xb84
Same here
> +#define MARGINING_IND_ERROR_SAMPLER BIT(28)
> +#define MARGINING_SAMPLE_REPORTING_METHOD BIT(27)
> +#define MARGINING_IND_LEFT_RIGHT_TIMING BIT(26)
> +#define MARGINING_IND_UP_DOWN_VOLTAGE BIT(25)
> +#define MARGINING_VOLTAGE_SUPPORTED BIT(24)
> +#define MARGINING_MAXLANES GENMASK(20, 16)
> +#define MARGINING_SAMPLE_RATE_TIMING GENMASK(13, 8)
> +#define MARGINING_SAMPLE_RATE_VOLTAGE GENMASK(5, 0)
> /*
> * iATU Unroll-specific register definitions
> * From 4.80 core version the address translation will be made by unroll
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c
> index dc7d93db9dc5..99b75e7f085d 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-common.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c
> @@ -43,3 +43,34 @@ void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci)
> dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
> }
> EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_eq_settings);
> +
> +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci)
I'd try to find a shorter symbol name here, "settings" seems redundant
after "set". Perhaps just
qcom_pcie_common_enable_lane_margining()
or
qcom_pcie_common_enable_16gt_lane_margining()?
if these settings are indeed specific to 16 GT/s. But perhaps it's
better to let the helper honour pci->max_link_speed if different
settings will later be needed for higher speeds:
if (pcie_link_speed[pci->max_link_speed] >= PCIE_SPEED_16_0GT)
qcom_pcie_common_enable_lane_margining(pci)
> void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci);
> +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci);
And maybe something similar for the eq settings for symmetry.
Johan
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