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Message-ID: <bf114807-c56c-4209-ab26-9e90ac00cedf@kernel.org>
Date: Thu, 5 Sep 2024 15:47:35 +0200
From: Konrad Dybcio <konradybcio@...nel.org>
To: Sricharan R <quic_srichara@...cinc.com>, bhelgaas@...gle.com,
lpieralisi@...nel.org, kw@...ux.com, manivannan.sadhasivam@...aro.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, vkoul@...nel.org,
kishon@...nel.org, andersson@...nel.org, konradybcio@...nel.org,
p.zabel@...gutronix.de, dmitry.baryshkov@...aro.org,
quic_nsekar@...cinc.com, linux-arm-msm@...r.kernel.org,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
robimarko@...il.com
Subject: Re: [PATCH V3 3/6] phy: qcom: Introduce PCIe UNIPHY 28LP driver
On 30.08.2024 10:11 AM, Sricharan R wrote:
> From: Nitheesh Sekar <quic_nsekar@...cinc.com>
>
> Add Qualcomm PCIe UNIPHY 28LP driver support present
> in Qualcomm IPQ5018 SoC and the phy init sequence.
>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@...cinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> ---
[...]
> +static const struct qcom_uniphy_pcie_data ipq5018_2x1_data = {
> + .lanes = 1,
> + .lane_offset = 0x800,
> + .phy_type = PHY_TYPE_PCIE_GEN2,
> + .init_seq = ipq5018_regs,
> + .init_seq_num = ARRAY_SIZE(ipq5018_regs),
> +};
> +
> +static const struct qcom_uniphy_pcie_data ipq5018_2x2_data = {
> + .lanes = 2,
> + .lane_offset = 0x800,
> + .phy_type = PHY_TYPE_PCIE_GEN2,
> + .init_seq = ipq5018_regs,
> + .init_seq_num = ARRAY_SIZE(ipq5018_regs),
> +};
As krzk suggested, the difference is just num-lanes
[...]
> +static int qcom_uniphy_pcie_power_off(struct phy *x)
> +{
> + struct qcom_uniphy_pcie *phy = phy_get_drvdata(x);
> +
> + reset_control_assert(phy->resets);
Is the reset line supposed to be kept asserted?
[...]
> +MODULE_LICENSE("Dual BSD/GPL");
Was that intended?
Konrad
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