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Message-ID: <ZtnVWrGdyotGDA7J@BLRRASHENOY1.amd.com>
Date: Thu, 5 Sep 2024 21:29:22 +0530
From: "Gautham R. Shenoy" <gautham.shenoy@....com>
To: Mario Limonciello <superm1@...nel.org>
Cc: Borislav Petkov <bp@...en8.de>, Perry Yuan <perry.yuan@....com>,
"maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@...nel.org>,
"Rafael J . Wysocki" <rafael@...nel.org>,
"open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <linux-kernel@...r.kernel.org>,
"open list:ACPI" <linux-acpi@...r.kernel.org>,
"open list:CPU FREQUENCY SCALING FRAMEWORK" <linux-pm@...r.kernel.org>,
Mario Limonciello <mario.limonciello@....com>
Subject: Re: [PATCH v2 08/11] cpufreq: amd-pstate: Merge
amd_pstate_highest_perf_set() into amd_get_boost_ratio_numerator()
On Tue, Sep 03, 2024 at 03:36:58PM -0500, Mario Limonciello wrote:
> From: Mario Limonciello <mario.limonciello@....com>
>
> The special case in amd_pstate_highest_perf_set() is the value used
> for calculating the boost numerator. Merge this into
> amd_get_boost_ratio_numerator() and then use that to calculate boost
> ratio.
>
> This allows dropping more special casing of the highest perf value.
>
> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
> ---
> v1->v2:
> * Document that preferred cores will have different values for highest
> perf.
> * Fix an uninitialized variable caused by merge
> ---
> Documentation/admin-guide/pm/amd-pstate.rst | 3 +-
> arch/x86/kernel/acpi/cppc.c | 16 +++++++
> drivers/cpufreq/amd-pstate.c | 52 ++++-----------------
> 3 files changed, 28 insertions(+), 43 deletions(-)
>
> diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst
> index d0324d44f5482..e13915c540648 100644
> --- a/Documentation/admin-guide/pm/amd-pstate.rst
> +++ b/Documentation/admin-guide/pm/amd-pstate.rst
> @@ -251,7 +251,8 @@ performance supported in `AMD CPPC Performance Capability <perf_cap_>`_).
> In some ASICs, the highest CPPC performance is not the one in the ``_CPC``
> table, so we need to expose it to sysfs. If boost is not active, but
> still supported, this maximum frequency will be larger than the one in
> -``cpuinfo``.
> +``cpuinfo``. On systems that support preferred core, the driver will have
> +different values for some cores than others.
Thanks for documenting this.
The patch looks good to me.
Reviewed-by: Gautham R. Shenoy <gautham.shenoy@....com>
--
Thanks and Regards
gautham.
> This attribute is read-only.
>
> ``amd_pstate_lowest_nonlinear_freq``
> diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c
> index df367bc359308..956984054bf30 100644
> --- a/arch/x86/kernel/acpi/cppc.c
> +++ b/arch/x86/kernel/acpi/cppc.c
> @@ -9,6 +9,7 @@
> #include <asm/processor.h>
> #include <asm/topology.h>
>
> +#define CPPC_HIGHEST_PERF_PERFORMANCE 196
> #define CPPC_HIGHEST_PERF_PREFCORE 166
>
> enum amd_pref_core {
> @@ -245,6 +246,21 @@ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator)
> *numerator = boost_numerator;
> return 0;
> }
> +
> + /*
> + * For AMD CPUs with Family ID 19H and Model ID range 0x70 to 0x7f,
> + * the highest performance level is set to 196.
> + * https://bugzilla.kernel.org/show_bug.cgi?id=218759
> + */
> + if (cpu_feature_enabled(X86_FEATURE_ZEN4)) {
> + switch (boot_cpu_data.x86_model) {
> + case 0x70 ... 0x7f:
> + *numerator = CPPC_HIGHEST_PERF_PERFORMANCE;
> + return 0;
> + default:
> + break;
> + }
> + }
> *numerator = CPPC_HIGHEST_PERF_PREFCORE;
>
> return 0;
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index c29cdf2d3882c..3ae41af6f041e 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -52,8 +52,6 @@
> #define AMD_PSTATE_TRANSITION_LATENCY 20000
> #define AMD_PSTATE_TRANSITION_DELAY 1000
> #define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600
> -#define CPPC_HIGHEST_PERF_PERFORMANCE 196
> -#define CPPC_HIGHEST_PERF_DEFAULT 166
>
> #define AMD_CPPC_EPP_PERFORMANCE 0x00
> #define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80
> @@ -372,43 +370,17 @@ static inline int amd_pstate_enable(bool enable)
> return static_call(amd_pstate_enable)(enable);
> }
>
> -static u32 amd_pstate_highest_perf_set(struct amd_cpudata *cpudata)
> -{
> - struct cpuinfo_x86 *c = &cpu_data(0);
> -
> - /*
> - * For AMD CPUs with Family ID 19H and Model ID range 0x70 to 0x7f,
> - * the highest performance level is set to 196.
> - * https://bugzilla.kernel.org/show_bug.cgi?id=218759
> - */
> - if (c->x86 == 0x19 && (c->x86_model >= 0x70 && c->x86_model <= 0x7f))
> - return CPPC_HIGHEST_PERF_PERFORMANCE;
> -
> - return CPPC_HIGHEST_PERF_DEFAULT;
> -}
> -
> static int pstate_init_perf(struct amd_cpudata *cpudata)
> {
> u64 cap1;
> - u32 highest_perf;
>
> int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
> &cap1);
> if (ret)
> return ret;
>
> - /* For platforms that do not support the preferred core feature, the
> - * highest_pef may be configured with 166 or 255, to avoid max frequency
> - * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as
> - * the default max perf.
> - */
> - if (cpudata->hw_prefcore)
> - highest_perf = amd_pstate_highest_perf_set(cpudata);
> - else
> - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
> -
> - WRITE_ONCE(cpudata->highest_perf, highest_perf);
> - WRITE_ONCE(cpudata->max_limit_perf, highest_perf);
> + WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
> + WRITE_ONCE(cpudata->max_limit_perf, AMD_CPPC_HIGHEST_PERF(cap1));
> WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
> WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));
> WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1));
> @@ -420,19 +392,13 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
> static int cppc_init_perf(struct amd_cpudata *cpudata)
> {
> struct cppc_perf_caps cppc_perf;
> - u32 highest_perf;
>
> int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
> if (ret)
> return ret;
>
> - if (cpudata->hw_prefcore)
> - highest_perf = amd_pstate_highest_perf_set(cpudata);
> - else
> - highest_perf = cppc_perf.highest_perf;
> -
> - WRITE_ONCE(cpudata->highest_perf, highest_perf);
> - WRITE_ONCE(cpudata->max_limit_perf, highest_perf);
> + WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf);
> + WRITE_ONCE(cpudata->max_limit_perf, cppc_perf.highest_perf);
> WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
> WRITE_ONCE(cpudata->lowest_nonlinear_perf,
> cppc_perf.lowest_nonlinear_perf);
> @@ -905,8 +871,8 @@ static u32 amd_pstate_get_transition_latency(unsigned int cpu)
> static int amd_pstate_init_freq(struct amd_cpudata *cpudata)
> {
> int ret;
> - u32 min_freq;
> - u32 highest_perf, max_freq;
> + u32 min_freq, max_freq;
> + u64 numerator;
> u32 nominal_perf, nominal_freq;
> u32 lowest_nonlinear_perf, lowest_nonlinear_freq;
> u32 boost_ratio, lowest_nonlinear_ratio;
> @@ -928,8 +894,10 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpudata)
>
> nominal_perf = READ_ONCE(cpudata->nominal_perf);
>
> - highest_perf = READ_ONCE(cpudata->highest_perf);
> - boost_ratio = div_u64(highest_perf << SCHED_CAPACITY_SHIFT, nominal_perf);
> + ret = amd_get_boost_ratio_numerator(cpudata->cpu, &numerator);
> + if (ret)
> + return ret;
> + boost_ratio = div_u64(numerator << SCHED_CAPACITY_SHIFT, nominal_perf);
> max_freq = (nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT) * 1000;
>
> lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf);
> --
> 2.43.0
>
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