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Message-ID: <CAJ+vNU3ZsJG-eoqf3JcHTyDwjp4uOW1XiEhnOfWZ1FJ-q1Y9Hw@mail.gmail.com>
Date: Thu, 5 Sep 2024 11:56:41 -0700
From: Tim Harvey <tharvey@...eworks.com>
To: Frank Li <Frank.Li@....com>
Cc: Shawn Guo <shawnguo@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>, Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, imx@...ts.linux.dev
Subject: Re: [PATCH v2 3/6] arm64: dts: imx8mm-venice-gw7901: add
#address(size)-cells for gsc@20
On Wed, Aug 7, 2024 at 7:54 AM Frank Li <Frank.Li@....com> wrote:
>
> Add #address-cells and #size-cells for gsc@20 to fix below warning:
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dtb: gsc@20: '#address-cells' is a required propert
>
> Signed-off-by: Frank Li <Frank.Li@....com>
> ---
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> index 136cb30df03a6..35ae0faa815bc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> @@ -364,6 +364,8 @@ gsc: gsc@20 {
> interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
> interrupt-controller;
> #interrupt-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
>
> adc {
> compatible = "gw,gsc-adc";
>
> --
> 2.34.1
>
>
Hi Frank,
I just noticed this patch (along with a few others to
imx8m*venice*dts* which undoes what was done in commit 3343ab4cc698
"arm64: dts: freescale: imx8m*-venice-*: fix gw,gsc dt-schema
warnings" which my commit message states: Fix the dt-schema warnings
due to #address-cells/#size-cells being unnecessary when there are no
children with reg cells.
With your patch applied I now see warnings again:
$ touch arch/arm64/boot/dts/freescale/imx8m*venice*.dts*; make dtbs W=1
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx-0x.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dtb
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts:361.14-467.4:
Warning (avoid_unnecessary_addr_size): /soc@...us@...00000/i2c@3
0a20000/gsc@20: unnecessary #address-cells/#size-cells without
"ranges", "dma-ranges" or child "reg" property
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dtb
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts:311.14-418.4:
Warning (avoid_unnecessary_addr_size): /soc@...us@...00000/i2c@3
0a20000/gsc@20: unnecessary #address-cells/#size-cells without
"ranges", "dma-ranges" or child "reg" property
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dtb
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts:277.14-364.4:
Warning (avoid_unnecessary_addr_size): /soc@...us@...00000/i2c@3
0a20000/gsc@20: unnecessary #address-cells/#size-cells without
"ranges", "dma-ranges" or child "reg" property
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dtb
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts:330.14-411.4:
Warning (avoid_unnecessary_addr_size): /soc@...us@...00000/i2c@3
0a20000/gsc@20: unnecessary #address-cells/#size-cells without
"ranges", "dma-ranges" or child "reg" property
DTC arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dtb
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts:309.14-416.4:
Warning (avoid_unnecessary_addr_size): /soc@...us@...00000/i2c@3
0a20000/gsc@20: unnecessary #address-cells/#size-cells without
"ranges", "dma-ranges" or child "reg" property
arch/arm64/boot/dts/freescale/imx8mn.dtsi:1128.11-1138.7: Warning
(graph_child_address): /soc@...us@...00000/isi@...20000/ports: grap
h node has single child node 'port@0', #address-cells/#size-cells are
not necessary
DTC arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dtb
DTC arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx-2x.dtb
DTC arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx-2x.dtb
DTC arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dtb
DTC arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx-2x.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtbo
DTOVL arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rpidsi.dtbo
DTOVL arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rpidsi.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtbo
DTOVL arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtbo
DTOVL arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtbo
DTOVL arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtbo
DTOVL arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rpidsi.dtbo
DTOVL arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rpidsi.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtbo
DTOVL arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtbo
DTOVL arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtb
DTC arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtbo
DTOVL arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtb
DTC arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtbo
DTOVL arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtb
DTC arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-rpidsi.dtbo
DTOVL arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-rpidsi.dtb
Is this some case of dueling dt-schema checks for dtb checks?
Best Regards,
Tim
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