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Message-ID: <t2mqfu62xx5uztlintofp4pquv6jalzace6w5jpymyyarb2wmn@vvo23e4cmu57>
Date: Thu, 5 Sep 2024 08:32:15 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Jan Kiszka <jan.kiszka@...mens.com>
Cc: Nishanth Menon <nm@...com>, Santosh Shilimkar <ssantosh@...nel.org>,
Vignesh Raghavendra <vigneshr@...com>, Tero Kristo <kristo@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-pci@...r.kernel.org,
Siddharth Vadapalli <s-vadapalli@...com>, Bao Cheng Su <baocheng.su@...mens.com>,
Hua Qian Li <huaqian.li@...mens.com>, Diogo Ivo <diogo.ivo@...mens.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>, Krzysztof Wilczyński <kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH v4 2/7] dt-bindings: PCI: ti,am65: Extend for use with PVU
On Wed, Sep 04, 2024 at 12:00:11PM +0200, Jan Kiszka wrote:
> From: Jan Kiszka <jan.kiszka@...mens.com>
>
> The PVU on the AM65 SoC is capable of restricting DMA from PCIe devices
> to specific regions of host memory. Add the optional property
> "memory-regions" to point to such regions of memory when PVU is used.
>
> Since the PVU deals with system physical addresses, utilizing the PVU
> with PCIe devices also requires setting up the VMAP registers to map the
> Requester ID of the PCIe device to the CBA Virtual ID, which in turn is
> mapped to the system physical address. Hence, describe the VMAP
> registers which are optionally unless the PVU shall used for PCIe.
>
> Signed-off-by: Jan Kiszka <jan.kiszka@...mens.com>
> ---
> CC: Lorenzo Pieralisi <lpieralisi@...nel.org>
> CC: "Krzysztof Wilczyński" <kw@...ux.com>
> CC: Bjorn Helgaas <bhelgaas@...gle.com>
> CC: linux-pci@...r.kernel.org
> ---
> .../bindings/pci/ti,am65-pci-host.yaml | 52 ++++++++++++++-----
> 1 file changed, 40 insertions(+), 12 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
> index 0a9d10532cc8..d8182bad92de 100644
> --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
> +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
> @@ -19,16 +19,6 @@ properties:
> - ti,am654-pcie-rc
> - ti,keystone-pcie
>
> - reg:
> - maxItems: 4
> -
> - reg-names:
> - items:
> - - const: app
> - - const: dbics
> - - const: config
> - - const: atu
Nothing improved here.
> -
> interrupts:
> maxItems: 1
>
> @@ -84,12 +74,48 @@ if:
> enum:
> - ti,am654-pcie-rc
> then:
> + properties:
> + reg:
> + minItems: 4
> + maxItems: 6
> +
> + reg-names:
> + minItems: 4
> + items:
> + - const: app
> + - const: dbics
> + - const: config
> + - const: atu
> + - const: vmap_lp
> + - const: vmap_hp
> +
> + memory-region:
> + minItems: 1
Missing maxItems
> + description: |
> + phandle to one or more restricted DMA pools to be used for all devices
> + behind this controller. The regions should be defined according to
> + reserved-memory/shared-dma-pool.yaml.
> + items:
> + maxItems: 1
And this feels redundant.
Best regards,
Krzysztof
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