linux-kernel - Re: [PATCH v6 3/4] PCI: qcom: Add equalization settings for 16.0 GT/s

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Message-ID: <ZtlUu3uwl06E7LJF@hovoldconsulting.com>
Date: Thu, 5 Sep 2024 08:50:35 +0200
From: Johan Hovold <johan@...nel.org>
To: Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
	Richard Zhu <hongxing.zhu@....com>,
	Lucas Stach <l.stach@...gutronix.de>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof Wilczyński <kw@...ux.com>,
	Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
	Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>,
	Jingoo Han <jingoohan1@...il.com>,
	Chuanhua Lei <lchuanhua@...linear.com>,
	Marek Vasut <marek.vasut+renesas@...il.com>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
	linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	imx@...ts.linux.dev, linux-kernel@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org, linux-arm-msm@...r.kernel.org,
	abel.vesa@...aro.org, johan+linaro@...nel.org
Subject: Re: [PATCH v6 3/4] PCI: qcom: Add equalization settings for 16.0 GT/s

On Wed, Sep 04, 2024 at 01:46:09PM -0700, Shashank Babu Chinta Venkata wrote:
> On 9/4/24 08:52, Manivannan Sadhasivam wrote:
> > On Wed, Sep 04, 2024 at 11:39:09AM +0200, Johan Hovold wrote:
> >> On Wed, Sep 04, 2024 at 12:41:59PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> >>> From: Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>

> >>> +	/*
> >>> +	 * GEN3_RELATED_OFF register is repurposed to apply equalization
> >>> +	 * settings at various data transmission rates through registers namely
> >>> +	 * GEN3_EQ_*. RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF determines
> >>> +	 * data rate for which this equalization settings are applied.

> >>> +	reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, 0x1);
> >>
> >> How does 0x1 map to gen4/16 GT?

> GEN3_RELATED_OFF has been repurposed to use with multiple data rates.
> RATE_SHADOW_SEL_MASK on GEN3_RELATED_OFF value decides the data rate
> of shadow registers namely GEN3_EQ_* registers. Per documentation 0x0
> maps to 8 GT/s, 0x1 maps to 16 GT/s and 0x2 maps to 32 GT/s. 

Thanks for clarifying. Perhaps these should become defines eventually
(or the comment could be extended). There are a lot of "magic" constants
in here.

Johan