| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20240906171449.324354-2-towinchenmi@gmail.com> Date: Sat, 7 Sep 2024 01:13:24 +0800 From: Nick Chan <towinchenmi@...il.com> To: Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org Cc: asahi@...ts.linux.dev, ~postmarketos/upstreaming@...ts.sr.ht, Nick Chan <towinchenmi@...il.com> Subject: [PATCH RESEND 1/2] arm64: cputype: Add CPU types for A7-A11, T2 SoCs A10(X), T2 types will be used soon, and the rest are added for documentation purposes. The A9 is made in two different fabs and those have different part numbers, and the TSMC cores are also used in A9X, so it cannot use the usual naming scheme. The A10(X), T2 performance/efficiency core pairs appears as single logical cores to software, so both the performance and efficiency core codenames needs to be included. Signed-off-by: Nick Chan <towinchenmi@...il.com> --- arch/arm64/include/asm/cputype.h | 42 +++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 5a7dfeb8e8eb..f1720158a54f 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -129,18 +129,27 @@ #define HISI_CPU_PART_TSV110 0xD01 -#define APPLE_CPU_PART_M1_ICESTORM 0x022 -#define APPLE_CPU_PART_M1_FIRESTORM 0x023 -#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024 -#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025 -#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028 -#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 -#define APPLE_CPU_PART_M2_BLIZZARD 0x032 -#define APPLE_CPU_PART_M2_AVALANCHE 0x033 -#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034 -#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035 -#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038 -#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039 +#define APPLE_CPU_PART_A7_CYCLONE 0x1 +#define APPLE_CPU_PART_A8_TYPHOON 0x2 +#define APPLE_CPU_PART_A8X_TYPHOON 0x3 +#define APPLE_CPU_PART_SAMSUNG_TWISTER 0x4 /* Used in Samsung A9 */ +#define APPLE_CPU_PART_TSMC_TWISTER 0x5 /* Used in TSMC A9 and A9X */ +#define APPLE_CPU_PART_A10_T2_HURRICANE_ZEPHYR 0x6 +#define APPLE_CPU_PART_A10X_HURRICANE_ZEPHYR 0x7 +#define APPLE_CPU_PART_A11_MONSOON 0x8 +#define APPLE_CPU_PART_A11_MISTRAL 0x9 +#define APPLE_CPU_PART_M1_ICESTORM 0x022 +#define APPLE_CPU_PART_M1_FIRESTORM 0x023 +#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024 +#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025 +#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028 +#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 +#define APPLE_CPU_PART_M2_BLIZZARD 0x032 +#define APPLE_CPU_PART_M2_AVALANCHE 0x033 +#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034 +#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035 +#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038 +#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039 #define AMPERE_CPU_PART_AMPERE1 0xAC3 #define AMPERE_CPU_PART_AMPERE1A 0xAC4 @@ -200,6 +209,15 @@ #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) +#define MIDR_APPLE_A7_CYCLONE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A7_CYCLONE) +#define MIDR_APPLE_A8_TYPHOON MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A8_TYPHOON) +#define MIDR_APPLE_A8X_TYPHOON MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A8X_TYPHOON) +#define MIDR_APPLE_SAMSUNG_TWISTER MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_SAMSUNG_TWISTER) +#define MIDR_APPLE_TSMC_TWISTER MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_TSMC_TWISTER) +#define MIDR_APPLE_A10_T2_HURRICANE_ZEPHYR MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A10_T2_HURRICANE_ZEPHYR) +#define MIDR_APPLE_A10X_HURRICANE_ZEPHYR MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A10X_HURRICANE_ZEPHYR) +#define MIDR_APPLE_A11_MONSOON MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A11_MONSOON) +#define MIDR_APPLE_A11_MISTRAL MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A11_MISTRAL) #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM) #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) #define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO) -- 2.46.0
Powered by blists - more mailing lists