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Message-ID: <mhng-64eec780-df98-4e8d-bf6c-0aa07a8d85da@palmer-ri-x1c9>
Date: Fri, 06 Sep 2024 11:48:03 -0700 (PDT)
From: Palmer Dabbelt <palmer@...belt.com>
To: namcao@...utronix.de
CC: bigeasy@...utronix.de, tglx@...utronix.de, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org, x86@...nel.org, hpa@...or.com,
aou@...s.berkeley.edu, bp@...en8.de, Catalin Marinas <catalin.marinas@....com>, williams@...hat.com,
dave.hansen@...ux.intel.com, mingo@...hat.com, john.ogness@...utronix.de,
Paul Walmsley <paul.walmsley@...ive.com>, pmladek@...e.com, senozhatsky@...omium.org, rostedt@...dmis.org,
Will Deacon <will@...nel.org>
Subject: Re: [PATCH 3/3] riscv: Allow to enable PREEMPT_RT.
On Fri, 06 Sep 2024 08:13:24 PDT (-0700), namcao@...utronix.de wrote:
> On Fri, Sep 06, 2024 at 12:59:06PM +0200, Sebastian Andrzej Siewior wrote:
>> It is really time.
>>
>> riscv has all the required architecture related changes, that have been
>> identified over time, in order to enable PREEMPT_RT. With the recent
>> printk changes, the last known road block has been addressed.
>>
>> Allow to enable PREEMPT_RT on riscv.
>>
>> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@...utronix.de>
>
> With the printk patches applied:
>
> Tested-by: Nam Cao <namcao@...utronix.de> # Visionfive 2
Thanks. LMK if you guys want me to take this through the RISC-V tree,
but no big deal if you want it somewhere else -- and if there's some
dependencies already going in through some sort of RT tree maybe that's
just easier. So
Acked-by: Palmer Dabbelt <palmer@...osinc.com>
I don't have a test setup yet, but I figure it's a new feature so I'll
just flip it on as a config post-rc1. Presumably this just works in the
QEMU virt board, or is there some wizardry I'll need to copy?
> Best regards,
> Nam
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