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Message-ID: <c2555924-8669-4aec-addd-da54fa4d34e2@amlogic.com> Date: Fri, 6 Sep 2024 16:26:25 +0800 From: Chuan Liu <chuan.liu@...ogic.com> To: Jerome Brunet <jbrunet@...libre.com>, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@...nel.org> Cc: Neil Armstrong <neil.armstrong@...aro.org>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Kevin Hilman <khilman@...libre.com>, Martin Blumenstingl <martin.blumenstingl@...glemail.com>, linux-amlogic@...ts.infradead.org, linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH 2/4] clk: meson: c3: pll: hifi_pll frequency is not accurate On 2024/9/6 14:55, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Fri 06 Sep 2024 at 13:52, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@...nel.org> wrote: > >> From: Chuan Liu <chuan.liu@...ogic.com> > The patch title is not good. the clock innacurate ... Ok, but you are doing > something about it, right ? Plus just saying that is a bit vague. > > How about something like "fix frac maximum value" ? This what you are > doing, right ? Right, Fix in next version. >> The fractional denominator of C3's hifi_pll fractional multiplier is >> fixed to 100000, so flag CLK_MESON_PLL_FIXED_FRAC_MAX is added. >> >> Fixes: 8a9a129dc565 ("clk: meson: c3: add support for the C3 SoC PLL clock") >> Signed-off-by: Chuan Liu <chuan.liu@...ogic.com> >> --- >> drivers/clk/meson/c3-pll.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/clk/meson/c3-pll.c b/drivers/clk/meson/c3-pll.c >> index 32bd2ed9d304..a350173efe90 100644 >> --- a/drivers/clk/meson/c3-pll.c >> +++ b/drivers/clk/meson/c3-pll.c >> @@ -361,6 +361,7 @@ static struct clk_regmap hifi_pll_dco = { >> .range = &c3_gp0_pll_mult_range, >> .init_regs = c3_hifi_init_regs, >> .init_count = ARRAY_SIZE(c3_hifi_init_regs), >> + .flags = CLK_MESON_PLL_FIXED_FRAC_MAX, >> }, >> .hw.init = &(struct clk_init_data) { >> .name = "hifi_pll_dco", > -- > Jerome
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