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Message-ID: <20240906121308.5013-1-suravee.suthikulpanit@amd.com>
Date: Fri, 6 Sep 2024 12:13:03 +0000
From: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
To: <linux-kernel@...r.kernel.org>, <iommu@...ts.linux.dev>
CC: <joro@...tes.org>, <robin.murphy@....com>, <vasant.hegde@....com>,
<ubizjak@...il.com>, <jgg@...dia.com>, <jon.grimm@....com>,
<santosh.shukla@....com>, <pandoh@...gle.com>, <kumaranand@...gle.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@....com>
Subject: [PATCH v3 0/5] iommu/amd: Use 128-bit cmpxchg operation to update DTE
This series modifies current implementation to use 128-bit cmpxchg to update DTE
when needed as specified in the AMD I/O Virtualization Techonology (IOMMU)
Specification.
Changes in V3:
* Patch 2:
- Consolidate patch 2 and 3
- Change rw_semaphore to spin_lock
* Patch 3: Expand locking across 256-bit DTE read and update
* Patch 4: Fix clear_dte_entry()
* Patch 5: Consolidate amd_iommu_set_dirty_tracking() and set_dte_irq_entry() fixes
v2: https://lore.kernel.org/lkml/20240829180726.5022-1-suravee.suthikulpanit@amd.com/
v1 :https://lore.kernel.org/lkml/e937e26f-038a-6d01-76a9-76c86760ca4a@gmail.com/T/
Thanks,
Suravee
Suravee Suthikulpanit (5):
iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is not supported
iommu/amd: Introduce helper functions to access and update 256-bit DTE
iommu/amd: Modify set_dte_entry() to use 256-bit DTE helpers
iommu/amd: Modify clear_dte_entry() to avoid in-place update
iommu/amd: Do not update DTE in-place in amd_iommu_set_dirty_tracking
and set_dte_irq_entry
drivers/iommu/amd/amd_iommu_types.h | 8 +-
drivers/iommu/amd/init.c | 23 +--
drivers/iommu/amd/iommu.c | 272 +++++++++++++++++++---------
3 files changed, 201 insertions(+), 102 deletions(-)
--
2.34.1
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