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Message-ID: <3ebb955d-ca25-4bbc-bf55-1b3cf2e20525@linaro.org> Date: Fri, 6 Sep 2024 15:46:15 +0300 From: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org> To: Satya Priya Kakitapalli <quic_skakitap@...cinc.com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Bjorn Andersson <andersson@...nel.org> Cc: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, Ajit Pandey <quic_ajipan@...cinc.com>, Taniya Das <quic_tdas@...cinc.com>, Imran Shaik <quic_imrashai@...cinc.com>, Jagadeesh Kona <quic_jkona@...cinc.com>, Dan Carpenter <dan.carpenter@...aro.org>, Jon Hunter <jonathanh@...dia.com>, kernel test robot <lkp@...el.com> Subject: Re: [PATCH V3] clk: qcom: clk-alpha-pll: Simplify the zonda_pll_adjust_l_val() Hi Satya Priya, On 9/6/24 14:39, Satya Priya Kakitapalli wrote: > In zonda_pll_adjust_l_val() replace the divide operator with comparison > operator to fix below build error and smatch warning. > > drivers/clk/qcom/clk-alpha-pll.o: In function `clk_zonda_pll_set_rate': > clk-alpha-pll.c:(.text+0x45dc): undefined reference to `__aeabi_uldivmod' > > smatch warnings: > drivers/clk/qcom/clk-alpha-pll.c:2129 zonda_pll_adjust_l_val() warn: replace > divide condition '(remainder * 2) / prate' with '(remainder * 2) >= prate' > > Fixes: f4973130d255 ("clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL") > Reported-by: Jon Hunter <jonathanh@...dia.com> > Reported-by: kernel test robot <lkp@...el.com> > Reported-by: Dan Carpenter <dan.carpenter@...aro.org> > Closes: https://lore.kernel.org/r/202408110724.8pqbpDiD-lkp@intel.com/ > Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@...cinc.com> thank you for the updates. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org> > --- > drivers/clk/qcom/clk-alpha-pll.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index 019713c38f25..f9105443d7db 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -2176,10 +2176,8 @@ static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 > > quotient = rate; > remainder = do_div(quotient, prate); > - *l = quotient; > > - if ((remainder * 2) / prate) > - *l = *l + 1; > + *l = rate + (u32)(remainder * 2 >= prate); > } > > static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, -- Best wishes, Vladimir
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