lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <879b934827fe4cea995e8e20ba0a796f@siengine.com>
Date: Sun, 8 Sep 2024 02:56:14 +0000
From: Liu Kimriver/刘金河 <kimriver.liu@...ngine.com>
To: Andi Shyti <andi.shyti@...nel.org>
CC: "jarkko.nikula@...ux.intel.com" <jarkko.nikula@...ux.intel.com>,
        "andriy.shevchenko@...ux.intel.com" <andriy.shevchenko@...ux.intel.com>,
        "mika.westerberg@...ux.intel.com" <mika.westerberg@...ux.intel.com>,
        "jsd@...ihalf.com" <jsd@...ihalf.com>,
        "linux-i2c@...r.kernel.org"
	<linux-i2c@...r.kernel.org>,
        "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] i2c: designware: fix master is holding SCL low while
 ENABLE bit is disabled

Hi Andi
 I am sorry for not replying to questions in time, when I left the office early on Friday.
 I sincerely apologize to you again.

I will improve my response progress and follow Andy's suggestion. Thanks.
And will resend new patch V7 on Moday:
[PATCH V7] i2c: designware: fix master is holding SCL low while ENABLE bit is disabled

-----邮件原件-----
发件人: Andi Shyti <andi.shyti@...nel.org> 
发送时间: 2024年9月7日 5:35
收件人: Liu Kimriver/刘金河 <kimriver.liu@...ngine.com>
抄送: jarkko.nikula@...ux.intel.com; andriy.shevchenko@...ux.intel.com; mika.westerberg@...ux.intel.com; jsd@...ihalf.com; linux-i2c@...r.kernel.org; linux-kernel@...r.kernel.org
主题: Re: [PATCH] i2c: designware: fix master is holding SCL low while ENABLE bit is disabled

Hi Kimriver,

...

> diff --git a/drivers/i2c/busses/i2c-designware-common.c 
> b/drivers/i2c/busses/i2c-designware-common.c
> index e8a688d04aee..2b3398cd4382 100644
> --- a/drivers/i2c/busses/i2c-designware-common.c
> +++ b/drivers/i2c/busses/i2c-designware-common.c
> @@ -453,6 +453,17 @@ void __i2c_dw_disable(struct dw_i2c_dev *dev)
>  
>  	abort_needed = raw_intr_stats & DW_IC_INTR_MST_ON_HOLD;
>  	if (abort_needed) {
> +		if (!(enable & DW_IC_ENABLE_ENABLE)) {
> +			regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE);

>BTW, your patch doesn't compile. Please make sure that you have everything in place and please resend.

>This time I expect you to follow Andy's suggestion.

Sorry, I forget to merge DW_IC_ENABLE_ENABLE patch to here. I will update V7 patch on Monday,
[PATCH V7] i2c: designware: fix master is holding SCL low while ENABLE bit is disabled
I will update V7 patch on Monday which includes the following issues:
-------
V6->V7:
	1. add Subject versioning
	2. change fsleep(25) to usleep_range(25, 250)
	3. Add macro definition DW_iC_ENABLE_ENABLE for compiling error
------------------
Best Regards
Kimriver Liu

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ