linux-kernel - Re: [PATCH v2 3/3] rust: Enable for MIPS

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Message-ID: <alpine.DEB.2.21.2409101643210.60835@angie.orcam.me.uk>
Date: Tue, 10 Sep 2024 17:03:39 +0100 (BST)
From: "Maciej W. Rozycki" <macro@...am.me.uk>
To: Jiaxun Yang <jiaxun.yang@...goat.com>
cc: Masahiro Yamada <masahiroy@...nel.org>, 
    Nathan Chancellor <nathan@...nel.org>, Nicolas Schier <nicolas@...sle.eu>, 
    Richard Weinberger <richard@....at>, 
    Anton Ivanov <anton.ivanov@...bridgegreys.com>, 
    Johannes Berg <johannes@...solutions.net>, 
    Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, 
    Borislav Petkov <bp@...en8.de>, Dave Hansen <dave.hansen@...ux.intel.com>, 
    x86@...nel.org, "H. Peter Anvin" <hpa@...or.com>, 
    Miguel Ojeda <ojeda@...nel.org>, Alex Gaynor <alex.gaynor@...il.com>, 
    Wedson Almeida Filho <wedsonaf@...il.com>, 
    Boqun Feng <boqun.feng@...il.com>, Gary Guo <gary@...yguo.net>, 
    Björn Roy Baron <bjorn3_gh@...tonmail.com>, 
    Benno Lossin <benno.lossin@...ton.me>, 
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    Steven Rostedt <rostedt@...dmis.org>, 
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    Mark Rutland <mark.rutland@....com>, Jonathan Corbet <corbet@....net>, 
    Alex Shi <alexs@...nel.org>, Yanteng Si <siyanteng@...ngson.cn>, 
    Nick Desaulniers <ndesaulniers@...gle.com>, 
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    linux-kbuild@...r.kernel.org, linux-kernel@...r.kernel.org, 
    linux-um@...ts.infradead.org, rust-for-linux@...r.kernel.org, 
    "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>, 
    linux-trace-kernel@...r.kernel.org, linux-doc@...r.kernel.org, 
    llvm@...ts.linux.dev
Subject: Re: [PATCH v2 3/3] rust: Enable for MIPS

On Mon, 9 Sep 2024, Jiaxun Yang wrote:

> >> diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs
> >> index 863720777313..bbdf8a4dd169 100644
> >> --- a/scripts/generate_rust_target.rs
> >> +++ b/scripts/generate_rust_target.rs
> > [...]
> >> +        } else {
> >> +            ts.push("arch", "mips");
> >> +            cfg.get("TARGET_ISA_REV").map(|isa_rev| {
> >> +                let feature = match isa_rev.as_str() {
> >> +                    "1" => ",+mips32",
> >> +                    "2" => ",+mips32r2",
> >> +                    "5" => ",+mips32r5",
> >> +                    "6" => ",+mips32r6",
> >> +                    _ => ",+mips2",
> >
> >  What's the consequence of using `mips2' rather than `mips1' here?  How 
> > about other ISA revisions, e.g. `mips4' (that also applies to the 64BIT 
> > leg)?
> 
> LLVM's mips1 backend is a little bit broken beyond repair, so I tried to use mips2
> as a baseline. I should probably let HAVE_RUST depend on !CPU_R3000 to get it covered.

 GCC works just fine I suppose, just as with the other language frontends, 
doesn't it?

> We have no good way to tell ISA reversion prior to R1 just from Kconfig TARGET_ISA_REV,
> valid numbers for TARGET_ISA_REV are only 1, 2, 5, 6 from Kconfig.

 This approach doesn't work for some MIPS architecture processor configs 
anyway, e.g. what ISA revision will CPU_P5600 imply here?

 However if there's a need (and previously there wasn't), then I think it 
can be sorted in a straightforward way.  We have just a bunch of CPU_* 
settings and we can define corresponding ISA_* settings to select, e.g. 
ISA_MIPS1, ISA_MIPS3, ISA_MIPS32_R1, ISA_MIPS64_R6, and so on, based on 
information extracted from per-CPU_* `-march=' compilation flags from 
arch/mips/Makefile (possibly combined with ISA data obtained from 
GCC/binutils for said flags).

 It could be a bit tedious to write, but not a big challenge really, just 
mechanical work.

> Given that mips 2 and 3 binaries (Rust object files) can link run flawlessly on all pre-R6
> (despite R3000) hardware with matching bitness, they were chosen as fallback here.

 I'm fine with having a MIPS1/R3000 exception for broken LLVM, but I see 
no reason to disable it for GCC.

  Maciej