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Message-ID: <alpine.DEB.2.21.2409102318270.60835@angie.orcam.me.uk>
Date: Tue, 10 Sep 2024 23:28:18 +0100 (BST)
From: "Maciej W. Rozycki" <macro@...am.me.uk>
To: Jiaxun Yang <jiaxun.yang@...goat.com>
cc: Masahiro Yamada <masahiroy@...nel.org>, 
    Nathan Chancellor <nathan@...nel.org>, Nicolas Schier <nicolas@...sle.eu>, 
    Richard Weinberger <richard@....at>, 
    Anton Ivanov <anton.ivanov@...bridgegreys.com>, 
    Johannes Berg <johannes@...solutions.net>, 
    Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, 
    Borislav Petkov <bp@...en8.de>, Dave Hansen <dave.hansen@...ux.intel.com>, 
    x86@...nel.org, "H. Peter Anvin" <hpa@...or.com>, 
    Miguel Ojeda <ojeda@...nel.org>, Alex Gaynor <alex.gaynor@...il.com>, 
    Wedson Almeida Filho <wedsonaf@...il.com>, 
    Boqun Feng <boqun.feng@...il.com>, Gary Guo <gary@...yguo.net>, 
    Björn Roy Baron <bjorn3_gh@...tonmail.com>, 
    Benno Lossin <benno.lossin@...ton.me>, 
    Andreas Hindborg <a.hindborg@...sung.com>, 
    Alice Ryhl <aliceryhl@...gle.com>, 
    Thomas Bogendoerfer <tsbogend@...ha.franken.de>, 
    Steven Rostedt <rostedt@...dmis.org>, 
    Masami Hiramatsu <mhiramat@...nel.org>, 
    Mark Rutland <mark.rutland@....com>, Jonathan Corbet <corbet@....net>, 
    Alex Shi <alexs@...nel.org>, Yanteng Si <siyanteng@...ngson.cn>, 
    Nick Desaulniers <ndesaulniers@...gle.com>, 
    Bill Wendling <morbo@...gle.com>, Justin Stitt <justinstitt@...gle.com>, 
    linux-kbuild@...r.kernel.org, linux-kernel@...r.kernel.org, 
    linux-um@...ts.infradead.org, rust-for-linux@...r.kernel.org, 
    "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>, 
    linux-trace-kernel@...r.kernel.org, linux-doc@...r.kernel.org, 
    llvm@...ts.linux.dev
Subject: Re: [PATCH v2 3/3] rust: Enable for MIPS

On Tue, 10 Sep 2024, Jiaxun Yang wrote:

> >> We have no good way to tell ISA reversion prior to R1 just from Kconfig TARGET_ISA_REV,
> >> valid numbers for TARGET_ISA_REV are only 1, 2, 5, 6 from Kconfig.
> >
> >  This approach doesn't work for some MIPS architecture processor configs 
> > anyway, e.g. what ISA revision will CPU_P5600 imply here?
> 
> TARGET_ISA_REV will be set to 5 for CPU_P5600 (CPU_MIPSR5 will default to y
> on CPU_P5600, and CPU_MIPSR5 sets TARGET_ISA_REV to 5). 
> >
> >  However if there's a need (and previously there wasn't), then I think it 
> > can be sorted in a straightforward way.  We have just a bunch of CPU_* 
> > settings and we can define corresponding ISA_* settings to select, e.g. 
> > ISA_MIPS1, ISA_MIPS3, ISA_MIPS32_R1, ISA_MIPS64_R6, and so on, based on 
> > information extracted from per-CPU_* `-march=' compilation flags from 
> > arch/mips/Makefile (possibly combined with ISA data obtained from 
> > GCC/binutils for said flags).
> >
> >  It could be a bit tedious to write, but not a big challenge really, just 
> > mechanical work.
> 
> TARGET_ISA_REV is guaranteed to be aligned with CPU's supported ISA for now,
> so I see no reason to invent another set of symbols....

 Ah, OK then, I missed these bits, thanks for pointing them out.

 So we only need to define CPU_MIPS1, CPU_MIPS3, and CPU_MIPS4 settings
(we have no support for any MIPS II CPU; there was the R6000 only at that 
ISA level, exeedingly rare and unreliable) analogously to and along with 
the existing CPU_MIPSR1, CPU_MIPSR2, etc., which is even simpler.  They 
can then be used accordingly for TARGET_ISA_REV == 0, either directly or 
perhaps via an additional TARGET_LEGACY_ISA_REV setting.

  Maciej

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