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Message-ID: <202409101353.K4jjCjRN-lkp@intel.com> Date: Tue, 10 Sep 2024 13:53:53 +0800 From: kernel test robot <lkp@...el.com> To: Tony W Wang-oc <TonyWWang-oc@...oxin.com>, tglx@...utronix.de, mingo@...hat.com, bp@...en8.de, dave.hansen@...ux.intel.com, x86@...nel.org, hpa@...or.com, tony.luck@...el.com, linux-kernel@...r.kernel.org, linux-edac@...r.kernel.org Cc: oe-kbuild-all@...ts.linux.dev, CobeChen@...oxin.com, TimGuo@...oxin.com, LeoLiu-oc@...oxin.com, Lyle Li <LyleLi@...oxin.com> Subject: Re: [PATCH v1 3/3] x86/mce: Add CMCI storm switching support for Zhaoxin Hi Tony, kernel test robot noticed the following build errors: [auto build test ERROR on tip/x86/core] [also build test ERROR on tip/master linus/master v6.11-rc7 next-20240909] [cannot apply to tip/auto-latest] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Tony-W-Wang-oc/x86-mce-Add-centaur-vendor-to-support-Zhaoxin-MCA/20240909-192507 base: tip/x86/core patch link: https://lore.kernel.org/r/20240909104349.3349-4-TonyWWang-oc%40zhaoxin.com patch subject: [PATCH v1 3/3] x86/mce: Add CMCI storm switching support for Zhaoxin config: x86_64-buildonly-randconfig-001-20240910 (https://download.01.org/0day-ci/archive/20240910/202409101353.K4jjCjRN-lkp@intel.com/config) compiler: gcc-12 (Debian 12.2.0-14) 12.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240910/202409101353.K4jjCjRN-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@...el.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202409101353.K4jjCjRN-lkp@intel.com/ All errors (new ones prefixed by >>): ld: arch/x86/kernel/cpu/mce/severity.o: in function `mce_zhaoxin_feature_init': severity.c:(.text+0x2c0): multiple definition of `mce_zhaoxin_feature_init'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x1950): first defined here ld: arch/x86/kernel/cpu/mce/severity.o: in function `mce_zhaoxin_feature_clear': severity.c:(.text+0x2f0): multiple definition of `mce_zhaoxin_feature_clear'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x1980): first defined here ld: arch/x86/kernel/cpu/mce/severity.o: in function `mce_zhaoxin_handle_storm': >> severity.c:(.text+0x320): multiple definition of `mce_zhaoxin_handle_storm'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x19b0): first defined here ld: arch/x86/kernel/cpu/mce/genpool.o: in function `mce_zhaoxin_feature_init': genpool.c:(.text+0x10): multiple definition of `mce_zhaoxin_feature_init'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x1950): first defined here ld: arch/x86/kernel/cpu/mce/genpool.o: in function `mce_zhaoxin_feature_clear': genpool.c:(.text+0x40): multiple definition of `mce_zhaoxin_feature_clear'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x1980): first defined here ld: arch/x86/kernel/cpu/mce/genpool.o: in function `mce_zhaoxin_handle_storm': genpool.c:(.text+0x70): multiple definition of `mce_zhaoxin_handle_storm'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x19b0): first defined here ld: arch/x86/kernel/cpu/mce/amd.o: in function `mce_zhaoxin_feature_init': amd.c:(.text+0x1730): multiple definition of `mce_zhaoxin_feature_init'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x1950): first defined here ld: arch/x86/kernel/cpu/mce/amd.o: in function `mce_zhaoxin_feature_clear': amd.c:(.text+0x1760): multiple definition of `mce_zhaoxin_feature_clear'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x1980): first defined here ld: arch/x86/kernel/cpu/mce/amd.o: in function `mce_zhaoxin_handle_storm': amd.c:(.text+0x1790): multiple definition of `mce_zhaoxin_handle_storm'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x19b0): first defined here ld: arch/x86/kernel/cpu/mce/threshold.o: in function `mce_zhaoxin_feature_init': threshold.c:(.text+0x70): multiple definition of `mce_zhaoxin_feature_init'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x1950): first defined here ld: arch/x86/kernel/cpu/mce/threshold.o: in function `mce_zhaoxin_feature_clear': threshold.c:(.text+0xa0): multiple definition of `mce_zhaoxin_feature_clear'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x1980): first defined here ld: arch/x86/kernel/cpu/mce/threshold.o: in function `mce_zhaoxin_handle_storm': threshold.c:(.text+0xd0): multiple definition of `mce_zhaoxin_handle_storm'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x19b0): first defined here ld: arch/x86/kernel/cpu/mce/inject.o: in function `mce_zhaoxin_feature_init': inject.c:(.text+0xd80): multiple definition of `mce_zhaoxin_feature_init'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x1950): first defined here ld: arch/x86/kernel/cpu/mce/inject.o: in function `mce_zhaoxin_feature_clear': inject.c:(.text+0xdb0): multiple definition of `mce_zhaoxin_feature_clear'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x1980): first defined here ld: arch/x86/kernel/cpu/mce/inject.o: in function `mce_zhaoxin_handle_storm': inject.c:(.text+0xde0): multiple definition of `mce_zhaoxin_handle_storm'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x19b0): first defined here ld: arch/x86/kernel/cpu/mce/apei.o: in function `mce_zhaoxin_feature_init': apei.c:(.text+0xf0): multiple definition of `mce_zhaoxin_feature_init'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x1950): first defined here ld: arch/x86/kernel/cpu/mce/apei.o: in function `mce_zhaoxin_feature_clear': apei.c:(.text+0x120): multiple definition of `mce_zhaoxin_feature_clear'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x1980): first defined here ld: arch/x86/kernel/cpu/mce/apei.o: in function `mce_zhaoxin_handle_storm': apei.c:(.text+0x150): multiple definition of `mce_zhaoxin_handle_storm'; arch/x86/kernel/cpu/mce/core.o:core.c:(.text+0x19b0): first defined here -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
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