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Message-ID: <01020191db2e68dd-f46a7a3b-61d3-4f99-a449-5c9b86d667cb-000000@eu-west-1.amazonses.com>
Date: Tue, 10 Sep 2024 09:05:37 +0000
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: linux-pci@...r.kernel.org
Cc: ryder.lee@...iatek.com, jianjun.wang@...iatek.com, lpieralisi@...nel.org,
kw@...ux.com, robh@...nel.org, bhelgaas@...gle.com,
matthias.bgg@...il.com, linux-mediatek@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
kernel@...labora.com
Subject: Re: [PATCH 0/2] PCI: mediatek-gen3: Support limiting link speed and
width
Il 06/08/24 11:48, AngeloGioacchino Del Regno ha scritto:
> This series adds support for limiting the PCI-Express link speed
> (or PCIe gen restriction) and link width (number of lanes) in the
> pcie-mediatek-gen3 driver.
>
> The maximum supported pcie gen is read from the controller itself,
> so defining a max gen through platform data for each SoC is avoided.
>
> Both are done by adding support for the standard devicetree properties
> `max-link-speed` and `num-lanes`.
>
> Please note that changing the bindings is not required, as those do
> already allow specifying those properties for this controller.
>
> AngeloGioacchino Del Regno (2):
> PCI: mediatek-gen3: Add support for setting max-link-speed limit
> PCI: mediatek-gen3: Add support for restricting link width
>
> drivers/pci/controller/pcie-mediatek-gen3.c | 76 ++++++++++++++++++++-
> 1 file changed, 74 insertions(+), 2 deletions(-)
>
Gentle ping for this series.
Thanks,
Angelo.
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