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Message-ID: <20240910092652.13354-3-TonyWWang-oc@zhaoxin.com>
Date: Tue, 10 Sep 2024 17:26:51 +0800
From: Tony W Wang-oc <TonyWWang-oc@...oxin.com>
To: <tglx@...utronix.de>, <mingo@...hat.com>, <bp@...en8.de>,
<dave.hansen@...ux.intel.com>, <x86@...nel.org>, <hpa@...or.com>,
<tony.luck@...el.com>, <linux-kernel@...r.kernel.org>,
<linux-edac@...r.kernel.org>
CC: <CobeChen@...oxin.com>, <TimGuo@...oxin.com>, <LeoLiu-oc@...oxin.com>,
Lyle Li <LyleLi@...oxin.com>
Subject: [PATCH v2 2/3] x86/mce: Add zhaoxin.c to support Zhaoxin MCA
From: Lyle Li <LyleLi@...oxin.com>
For the sake of code standardization, add zhaoxin.c to
override the Zhaoxin MCA code.
Signed-off-by: Lyle Li <LyleLi@...oxin.com>
---
arch/x86/Kconfig | 8 +++++++
arch/x86/kernel/cpu/mce/Makefile | 2 +-
arch/x86/kernel/cpu/mce/core.c | 28 ------------------------
arch/x86/kernel/cpu/mce/internal.h | 7 ++++++
arch/x86/kernel/cpu/mce/zhaoxin.c | 35 ++++++++++++++++++++++++++++++
5 files changed, 51 insertions(+), 29 deletions(-)
create mode 100644 arch/x86/kernel/cpu/mce/zhaoxin.c
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1d7122a18..b908cdfb9 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1171,6 +1171,14 @@ config X86_MCE_INTEL
Additional support for intel specific MCE features such as
the thermal monitor.
+config X86_MCE_ZHAOXIN
+ def_bool y
+ prompt "Zhaoxin MCE features"
+ depends on X86_MCE_INTEL
+ help
+ Additional support for zhaoxin specific MCE features such as
+ the corrected machine check interrupt.
+
config X86_MCE_AMD
def_bool y
prompt "AMD MCE features"
diff --git a/arch/x86/kernel/cpu/mce/Makefile b/arch/x86/kernel/cpu/mce/Makefile
index 015856abd..2e863e78d 100644
--- a/arch/x86/kernel/cpu/mce/Makefile
+++ b/arch/x86/kernel/cpu/mce/Makefile
@@ -5,7 +5,7 @@ obj-$(CONFIG_X86_ANCIENT_MCE) += winchip.o p5.o
obj-$(CONFIG_X86_MCE_INTEL) += intel.o
obj-$(CONFIG_X86_MCE_AMD) += amd.o
obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o
-
+obj-$(CONFIG_X86_MCE_ZHAOXIN) += zhaoxin.o
mce-inject-y := inject.o
obj-$(CONFIG_X86_MCE_INJECT) += mce-inject.o
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index b7b98c33a..b32bfd9f3 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -2028,34 +2028,6 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
}
}
-static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
-{
- struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
-
- /*
- * These CPUs have MCA bank 8 which reports only one error type called
- * SVAD (System View Address Decoder). The reporting of that error is
- * controlled by IA32_MC8.CTL.0.
- *
- * If enabled, prefetching on these CPUs will cause SVAD MCE when
- * virtual machines start and result in a system panic. Always disable
- * bank 8 SVAD error by default.
- */
- if ((c->x86 == 7 && c->x86_model == 0x1b) ||
- (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
- if (this_cpu_read(mce_num_banks) > 8)
- mce_banks[8].ctl = 0;
- }
-
- intel_init_cmci();
- intel_init_lmce();
-}
-
-static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
-{
- intel_clear_lmce();
-}
-
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h
index 01f8f0396..836e56027 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -334,4 +334,11 @@ static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg)
}
extern void (*mc_poll_banks)(void);
+#ifdef CONFIG_X86_MCE_ZHAOXIN
+void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c);
+void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c);
+#else
+static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { }
+static inline void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) { }
+#endif
#endif /* __X86_MCE_INTERNAL_H__ */
diff --git a/arch/x86/kernel/cpu/mce/zhaoxin.c b/arch/x86/kernel/cpu/mce/zhaoxin.c
new file mode 100644
index 000000000..97d12ce0c
--- /dev/null
+++ b/arch/x86/kernel/cpu/mce/zhaoxin.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Zhaoxin specific MCE features
+ * Author: Lyle Li
+ */
+#include <asm/msr.h>
+#include "internal.h"
+
+void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
+{
+ struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
+
+ /*
+ * These CPUs have MCA bank 8 which reports only one error type called
+ * SVAD (System View Address Decoder). The reporting of that error is
+ * controlled by IA32_MC8.CTL.0.
+ *
+ * If enabled, prefetching on these CPUs will cause SVAD MCE when
+ * virtual machines start and result in a system panic. Always disable
+ * bank 8 SVAD error by default.
+ */
+ if ((c->x86 == 7 && c->x86_model == 0x1b) ||
+ (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
+ if (this_cpu_read(mce_num_banks) > 8)
+ mce_banks[8].ctl = 0;
+ }
+
+ intel_init_cmci();
+ intel_init_lmce();
+}
+
+void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
+{
+ intel_clear_lmce();
+}
--
2.34.1
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