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Message-ID: <20240911135011.161217-3-hugues.fruchet@foss.st.com>
Date: Wed, 11 Sep 2024 15:50:11 +0200
From: Hugues Fruchet <hugues.fruchet@...s.st.com>
To: Mauro Carvalho Chehab <mchehab@...nel.org>,
Ezequiel Garcia
<ezequiel@...guardiasur.com.ar>,
Philipp Zabel <p.zabel@...gutronix.de>,
Hans
Verkuil <hverkuil-cisco@...all.nl>,
Fritz Koenig <frkoenig@...omium.org>,
Sebastian Fricke <sebastian.fricke@...labora.com>,
Daniel Almeida
<daniel.almeida@...labora.com>,
Andrzej Pietrasiewicz
<andrzej.p@...labora.com>,
Nicolas Dufresne <nicolas.dufresne@...labora.com>,
Benjamin Gaignard <benjamin.gaignard@...labora.com>,
<linux-media@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-rockchip@...ts.infradead.org>,
<linux-stm32@...md-mailman.stormreply.com>
CC: Hugues Fruchet <hugues.fruchet@...s.st.com>
Subject: [PATCH 2/2] media: verisilicon: add WebP decoding support
Add WebP picture decoding support to VP8 stateless decoder.
Signed-off-by: Hugues Fruchet <hugues.fruchet@...s.st.com>
---
drivers/media/platform/verisilicon/hantro_g1_regs.h | 1 +
drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/media/platform/verisilicon/hantro_g1_regs.h b/drivers/media/platform/verisilicon/hantro_g1_regs.h
index c623b3b0be18..e7d4db788e57 100644
--- a/drivers/media/platform/verisilicon/hantro_g1_regs.h
+++ b/drivers/media/platform/verisilicon/hantro_g1_regs.h
@@ -232,6 +232,7 @@
#define G1_REG_DEC_CTRL7_DCT7_START_BIT(x) (((x) & 0x3f) << 0)
#define G1_REG_ADDR_STR 0x030
#define G1_REG_ADDR_DST 0x034
+#define G1_REG_ADDR_DST_CHROMA 0x038
#define G1_REG_ADDR_REF(i) (0x038 + ((i) * 0x4))
#define G1_REG_ADDR_REF_FIELD_E BIT(1)
#define G1_REG_ADDR_REF_TOPC_E BIT(0)
diff --git a/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c b/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c
index 851eb67f19f5..c6a7584b716a 100644
--- a/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c
+++ b/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c
@@ -427,6 +427,11 @@ static void cfg_buffers(struct hantro_ctx *ctx,
dst_dma = hantro_get_dec_buf_addr(ctx, &vb2_dst->vb2_buf);
vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DST);
+
+ if (hdr->flags & V4L2_VP8_FRAME_FLAG_WEBP)
+ vdpu_write_relaxed(vpu, dst_dma +
+ ctx->dst_fmt.height * ctx->dst_fmt.width,
+ G1_REG_ADDR_DST_CHROMA);
}
int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx)
@@ -471,6 +476,8 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx)
reg |= G1_REG_DEC_CTRL0_SKIP_MODE;
if (hdr->lf.level == 0)
reg |= G1_REG_DEC_CTRL0_FILTERING_DIS;
+ if (hdr->flags & V4L2_VP8_FRAME_FLAG_WEBP)
+ reg |= G1_REG_DEC_CTRL0_WEBP_E;
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0);
/* Frame dimensions */
--
2.25.1
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