linux-kernel - Re: [PATCH 01/22] dt-bindings: arm: cpus: Add Apple A7-A11 CPU cores

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20240911-unsuited-pranker-60a7d0b6caf9@spud>
Date: Wed, 11 Sep 2024 19:16:46 +0100
From: Conor Dooley <conor@...nel.org>
To: Nick Chan <towinchenmi@...il.com>
Cc: Hector Martin <marcan@...can.st>, Sven Peter <sven@...npeter.dev>,
	Alyssa Rosenzweig <alyssa@...enzweig.io>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	"Rafael J . Wysocki" <rafael@...nel.org>,
	Viresh Kumar <viresh.kumar@...aro.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	Wim Van Sebroeck <wim@...ux-watchdog.org>,
	Guenter Roeck <linux@...ck-us.net>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will@...nel.org>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Mark Kettenis <kettenis@...nbsd.org>, asahi@...ts.linux.dev,
	linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
	linux-gpio@...r.kernel.org, linux-watchdog@...r.kernel.org,
	Konrad Dybcio <konradybcio@...nel.org>,
	Ivaylo Ivanov <ivo.ivanov.ivanov1@...il.com>
Subject: Re: [PATCH 01/22] dt-bindings: arm: cpus: Add Apple A7-A11 CPU cores

On Wed, Sep 11, 2024 at 04:40:51PM +0800, Nick Chan wrote:
> Add the following CPU cores:
> 
> - apple,cyclone: A7 cores
> - apple,typhoon: A8 cores
> - apple,twister: A9 cores
> - apple,hurricane-zephyr: A10 logical cores
> - apple,monsoon: A11 performance cores
> - apple,mistral: A11 efficiency cores
> 
> In the Apple A10, there are physical performance-efficiency cores that
> forms logical cores to software depending on the current p-state, and
> only one type of core may be active at one time.
> 
> Signed-off-by: Nick Chan <towinchenmi@...il.com>
> ---
>  Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> index f308ff6c3532..3959e022079f 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> @@ -89,6 +89,12 @@ properties:
>        - apple,blizzard
>        - apple,icestorm
>        - apple,firestorm
> +      - apple,mistral
> +      - apple,monsoon
> +      - apple,hurricane-zephyr
> +      - apple,twister
> +      - apple,typhoon
> +      - apple,cyclone

Same on this one, can you add these in alphanumerical order, even if the
existing 3 devices are not in it? You could take the opportunity to
reshuffle icestorm and firestorm while you're at it.

Cheers,
Conor.

>        - arm,arm710t
>        - arm,arm720t
>        - arm,arm740t
> -- 
> 2.46.0
> 

Download attachment "signature.asc" of type "application/pgp-signature" (229 bytes)