linux-kernel - Re: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs

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Message-ID: <cbc505ca-3df0-4139-87a1-db603f9f426a@lunn.ch>
Date: Thu, 12 Sep 2024 17:28:02 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Raju Lakkaraju <Raju.Lakkaraju@...rochip.com>
Cc: netdev@...r.kernel.org, davem@...emloft.net, edumazet@...gle.com,
	kuba@...nel.org, pabeni@...hat.com, bryan.whitehead@...rochip.com,
	UNGLinuxDriver@...rochip.com, linux@...linux.org.uk,
	maxime.chevallier@...tlin.com, rdunlap@...radead.org,
	Steen.Hegelund@...rochip.com, daniel.machon@...rochip.com,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs

> > Also, am i reading this correct. C22 transfers will go out a
> > completely different bus to C45 transfers when there is an SFP?
> 
> No. You are correct.
> This LAN743x driver support following chips
> 1. LAN7430 - C22 only with GMII/RGMII I/F
> 2. LAN7431 - C22 only with MII I/F

Fine, simple, not a problem.

> 3. PCI11010/PCI11414 - C45 with RGMII or SGMII/1000Base-X/2500Base-X
>    If SFP enable, then XPCS's C45 PCS access
>    If SGMII only enable, then SGMII (PCS) C45 access

Physically, there are two MDIO busses? There is an external MDIO bus
with two pins along side the RGMII/SGMII pins? And internally, there
is an MDIO bus to the PCS block?

Some designs do have only one bus, the internal PCS uses address X on
the bus and you are simply not allowed to put an external device at
that address.

But from my reading of the code, you have two MDIO busses, so you need
two Linux MDIO busses.

	Andrew