linux-kernel - Re: [PATCH v4 3/3] riscv: Call riscv_user_isa

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Message-ID: <ZuNyUC8mUSp8UtfI@ghost>
Date: Thu, 12 Sep 2024 15:59:28 -0700
From: Charlie Jenkins <charlie@...osinc.com>
To: Samuel Holland <samuel.holland@...ive.com>
Cc: linux-riscv@...ts.infradead.org, Palmer Dabbelt <palmer@...belt.com>,
	Andrew Jones <ajones@...tanamicro.com>,
	Conor Dooley <conor@...nel.org>, linux-kernel@...r.kernel.org,
	Deepak Gupta <debug@...osinc.com>,
	Conor Dooley <conor.dooley@...rochip.com>,
	Albert Ou <aou@...s.berkeley.edu>, Andy Chiu <andy.chiu@...ive.com>,
	Clément Léger <cleger@...osinc.com>,
	Evan Green <evan@...osinc.com>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Xiao Wang <xiao.w.wang@...el.com>, Zhao Ke <ke.zhao@...ngroup.cn>
Subject: Re: [PATCH v4 3/3] riscv: Call riscv_user_isa_enable() only on the
 boot hart

On Wed, Aug 14, 2024 at 01:10:56AM -0700, Samuel Holland wrote:
> Now that the [ms]envcfg CSR value is maintained per thread, not per
> hart, riscv_user_isa_enable() only needs to be called once during boot,
> to set the value for the init task. This also allows it to be marked as
> __init.
> 
> Reviewed-by: Andrew Jones <ajones@...tanamicro.com>
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
> Reviewed-by: Deepak Gupta <debug@...osinc.com>
> Signed-off-by: Samuel Holland <samuel.holland@...ive.com>

Reviewed-by: Charlie Jenkins <charlie@...osinc.com>

> ---
> 
> Changes in v4:
>  - Rebase on riscv/for-next (v6.11-rc)
>  - Add Conor's Reviewed-by tags from v2 (missed in v3)
> 
> Changes in v3:
>  - Drop use of __initdata due to conflicts with cpufeature.c refactoring
> 
> Changes in v2:
>  - Rebase on riscv/for-next
> 
>  arch/riscv/include/asm/cpufeature.h | 2 +-
>  arch/riscv/kernel/cpufeature.c      | 4 ++--
>  arch/riscv/kernel/smpboot.c         | 2 --
>  3 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 45f9c1171a48..ce9a995730c1 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -31,7 +31,7 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
>  /* Per-cpu ISA extensions. */
>  extern struct riscv_isainfo hart_isa[NR_CPUS];
>  
> -void riscv_user_isa_enable(void);
> +void __init riscv_user_isa_enable(void);
>  
>  #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _validate) {	\
>  	.name = #_name,									\
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index df3e7e8d6d78..b3b9735cb19a 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -919,12 +919,12 @@ unsigned long riscv_get_elf_hwcap(void)
>  	return hwcap;
>  }
>  
> -void riscv_user_isa_enable(void)
> +void __init riscv_user_isa_enable(void)
>  {
>  	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ))
>  		current->thread.envcfg |= ENVCFG_CBZE;
>  	else if (any_cpu_has_zicboz)
> -		pr_warn_once("Zicboz disabled as it is unavailable on some harts\n");
> +		pr_warn("Zicboz disabled as it is unavailable on some harts\n");
>  }
>  
>  #ifdef CONFIG_RISCV_ALTERNATIVE
> diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> index 0f8f1c95ac38..e36d20205bd7 100644
> --- a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -233,8 +233,6 @@ asmlinkage __visible void smp_callin(void)
>  	numa_add_cpu(curr_cpuid);
>  	set_cpu_online(curr_cpuid, true);
>  
> -	riscv_user_isa_enable();
> -
>  	/*
>  	 * Remote cache and TLB flushes are ignored while the CPU is offline,
>  	 * so flush them both right now just in case.
> -- 
> 2.45.1
>