[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240912231650.3740732-6-debug@rivosinc.com>
Date: Thu, 12 Sep 2024 16:16:24 -0700
From: Deepak Gupta <debug@...osinc.com>
To: paul.walmsley@...ive.com,
palmer@...ive.com,
conor@...nel.org,
linux-doc@...r.kernel.org,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
linux-fsdevel@...r.kernel.org,
linux-mm@...ck.org,
linux-arch@...r.kernel.org,
linux-kselftest@...r.kernel.org
Cc: corbet@....net,
palmer@...belt.com,
aou@...s.berkeley.edu,
robh@...nel.org,
krzk+dt@...nel.org,
oleg@...hat.com,
tglx@...utronix.de,
mingo@...hat.com,
bp@...en8.de,
dave.hansen@...ux.intel.com,
x86@...nel.org,
hpa@...or.com,
peterz@...radead.org,
akpm@...ux-foundation.org,
arnd@...db.de,
ebiederm@...ssion.com,
kees@...nel.org,
Liam.Howlett@...cle.com,
vbabka@...e.cz,
lorenzo.stoakes@...cle.com,
shuah@...nel.org,
brauner@...nel.org,
samuel.holland@...ive.com,
debug@...osinc.com,
andy.chiu@...ive.com,
jerry.shih@...ive.com,
greentime.hu@...ive.com,
charlie@...osinc.com,
evan@...osinc.com,
cleger@...osinc.com,
xiao.w.wang@...el.com,
ajones@...tanamicro.com,
anup@...infault.org,
mchitale@...tanamicro.com,
atishp@...osinc.com,
sameo@...osinc.com,
bjorn@...osinc.com,
alexghiti@...osinc.com,
david@...hat.com,
libang.li@...group.com,
jszhang@...nel.org,
leobras@...hat.com,
guoren@...nel.org,
samitolvanen@...gle.com,
songshuaishuai@...ylab.org,
costa.shul@...hat.com,
bhe@...hat.com,
zong.li@...ive.com,
puranjay@...nel.org,
namcaov@...il.com,
antonb@...storrent.com,
sorear@...tmail.com,
quic_bjorande@...cinc.com,
ancientmodern4@...il.com,
ben.dooks@...ethink.co.uk,
quic_zhonhan@...cinc.com,
cuiyunhui@...edance.com,
yang.lee@...ux.alibaba.com,
ke.zhao@...ngroup.cn,
sunilvl@...tanamicro.com,
tanzhasanwork@...il.com,
schwab@...e.de,
dawei.li@...ngroup.cn,
rppt@...nel.org,
willy@...radead.org,
usama.anjum@...labora.com,
osalvador@...e.de,
ryan.roberts@....com,
andrii@...nel.org,
alx@...nel.org,
catalin.marinas@....com,
broonie@...nel.org,
revest@...omium.org,
bgray@...ux.ibm.com,
deller@....de,
zev@...ilderbeest.net,
Conor Dooley <conor.dooley@...rochip.com>
Subject: [PATCH v4 05/30] riscv: Call riscv_user_isa_enable() only on the boot hart
From: Samuel Holland <samuel.holland@...ive.com>
Now that the [ms]envcfg CSR value is maintained per thread, not per
hart, riscv_user_isa_enable() only needs to be called once during boot,
to set the value for the init task. This also allows it to be marked as
__init.
Reviewed-by: Andrew Jones <ajones@...tanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Reviewed-by: Deepak Gupta <debug@...osinc.com>
Signed-off-by: Samuel Holland <samuel.holland@...ive.com>
Signed-off-by: Deepak Gupta <debug@...osinc.com>
---
arch/riscv/include/asm/cpufeature.h | 2 +-
arch/riscv/kernel/cpufeature.c | 4 ++--
arch/riscv/kernel/smpboot.c | 2 --
3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 45f9c1171a48..ce9a995730c1 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -31,7 +31,7 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
/* Per-cpu ISA extensions. */
extern struct riscv_isainfo hart_isa[NR_CPUS];
-void riscv_user_isa_enable(void);
+void __init riscv_user_isa_enable(void);
#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _validate) { \
.name = #_name, \
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index f7fcd23d55de..41fd0be25bd8 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -919,12 +919,12 @@ unsigned long riscv_get_elf_hwcap(void)
return hwcap;
}
-void riscv_user_isa_enable(void)
+void __init riscv_user_isa_enable(void)
{
if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ))
current->thread_info.envcfg |= ENVCFG_CBZE;
else if (any_cpu_has_zicboz)
- pr_warn_once("Zicboz disabled as it is unavailable on some harts\n");
+ pr_warn("Zicboz disabled as it is unavailable on some harts\n");
}
#ifdef CONFIG_RISCV_ALTERNATIVE
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 0f8f1c95ac38..e36d20205bd7 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -233,8 +233,6 @@ asmlinkage __visible void smp_callin(void)
numa_add_cpu(curr_cpuid);
set_cpu_online(curr_cpuid, true);
- riscv_user_isa_enable();
-
/*
* Remote cache and TLB flushes are ignored while the CPU is offline,
* so flush them both right now just in case.
--
2.45.0
Powered by blists - more mailing lists