lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240912231650.3740732-28-debug@rivosinc.com>
Date: Thu, 12 Sep 2024 16:16:46 -0700
From: Deepak Gupta <debug@...osinc.com>
To: paul.walmsley@...ive.com,
	palmer@...ive.com,
	conor@...nel.org,
	linux-doc@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-fsdevel@...r.kernel.org,
	linux-mm@...ck.org,
	linux-arch@...r.kernel.org,
	linux-kselftest@...r.kernel.org
Cc: corbet@....net,
	palmer@...belt.com,
	aou@...s.berkeley.edu,
	robh@...nel.org,
	krzk+dt@...nel.org,
	oleg@...hat.com,
	tglx@...utronix.de,
	mingo@...hat.com,
	bp@...en8.de,
	dave.hansen@...ux.intel.com,
	x86@...nel.org,
	hpa@...or.com,
	peterz@...radead.org,
	akpm@...ux-foundation.org,
	arnd@...db.de,
	ebiederm@...ssion.com,
	kees@...nel.org,
	Liam.Howlett@...cle.com,
	vbabka@...e.cz,
	lorenzo.stoakes@...cle.com,
	shuah@...nel.org,
	brauner@...nel.org,
	samuel.holland@...ive.com,
	debug@...osinc.com,
	andy.chiu@...ive.com,
	jerry.shih@...ive.com,
	greentime.hu@...ive.com,
	charlie@...osinc.com,
	evan@...osinc.com,
	cleger@...osinc.com,
	xiao.w.wang@...el.com,
	ajones@...tanamicro.com,
	anup@...infault.org,
	mchitale@...tanamicro.com,
	atishp@...osinc.com,
	sameo@...osinc.com,
	bjorn@...osinc.com,
	alexghiti@...osinc.com,
	david@...hat.com,
	libang.li@...group.com,
	jszhang@...nel.org,
	leobras@...hat.com,
	guoren@...nel.org,
	samitolvanen@...gle.com,
	songshuaishuai@...ylab.org,
	costa.shul@...hat.com,
	bhe@...hat.com,
	zong.li@...ive.com,
	puranjay@...nel.org,
	namcaov@...il.com,
	antonb@...storrent.com,
	sorear@...tmail.com,
	quic_bjorande@...cinc.com,
	ancientmodern4@...il.com,
	ben.dooks@...ethink.co.uk,
	quic_zhonhan@...cinc.com,
	cuiyunhui@...edance.com,
	yang.lee@...ux.alibaba.com,
	ke.zhao@...ngroup.cn,
	sunilvl@...tanamicro.com,
	tanzhasanwork@...il.com,
	schwab@...e.de,
	dawei.li@...ngroup.cn,
	rppt@...nel.org,
	willy@...radead.org,
	usama.anjum@...labora.com,
	osalvador@...e.de,
	ryan.roberts@....com,
	andrii@...nel.org,
	alx@...nel.org,
	catalin.marinas@....com,
	broonie@...nel.org,
	revest@...omium.org,
	bgray@...ux.ibm.com,
	deller@....de,
	zev@...ilderbeest.net
Subject: [PATCH v4 27/30] riscv: create a config for shadow stack and landing pad instr support

This patch creates a config for shadow stack support and landing pad instr
support. Shadow stack support and landing instr support can be enabled by
selecting `CONFIG_RISCV_USER_CFI`. Selecting `CONFIG_RISCV_USER_CFI` wires
up path to enumerate CPU support and if cpu support exists, kernel will
support cpu assisted user mode cfi.

If CONFIG_RISCV_USER_CFI is selected, select `ARCH_USES_HIGH_VMA_FLAGS`
and `ARCH_HAS_USER_SHADOW_STACK` for riscv.

Signed-off-by: Deepak Gupta <debug@...osinc.com>
---
 arch/riscv/Kconfig | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d1d629a3eb91..24bf08c905d2 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -231,6 +231,25 @@ config ARCH_HAS_BROKEN_DWARF5
 	# https://github.com/llvm/llvm-project/commit/7ffabb61a5569444b5ac9322e22e5471cc5e4a77
 	depends on LD_IS_LLD && LLD_VERSION < 180000
 
+config RISCV_USER_CFI
+	def_bool y
+	bool "riscv userspace control flow integrity"
+	depends on 64BIT && $(cc-option,-mabi=lp64 -march=rv64ima_zicfiss)
+	depends on RISCV_ALTERNATIVE
+	select ARCH_HAS_USER_SHADOW_STACK
+	select ARCH_USES_HIGH_VMA_FLAGS
+	help
+	  Provides CPU assisted control flow integrity to userspace tasks.
+	  Control flow integrity is provided by implementing shadow stack for
+	  backward edge and indirect branch tracking for forward edge in program.
+	  Shadow stack protection is a hardware feature that detects function
+	  return address corruption. This helps mitigate ROP attacks.
+	  Indirect branch tracking enforces that all indirect branches must land
+	  on a landing pad instruction else CPU will fault. This mitigates against
+	  JOP / COP attacks. Applications must be enabled to use it, and old user-
+	  space does not get protection "for free".
+	  default y
+
 config ARCH_MMAP_RND_BITS_MIN
 	default 18 if 64BIT
 	default 8
-- 
2.45.0


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ