lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20240913-starqltechn_integration_upstream-v4-2-2d2efd5c5877@gmail.com>
Date: Fri, 13 Sep 2024 18:07:45 +0300
From: Dzmitry Sankouski <dsankouski@...il.com>
To: Sebastian Reichel <sre@...nel.org>, 
 Bjorn Andersson <andersson@...nel.org>, 
 Michael Turquette <mturquette@...libre.com>, 
 Stephen Boyd <sboyd@...nel.org>, Neil Armstrong <neil.armstrong@...aro.org>, 
 Jessica Zhang <quic_jesszhan@...cinc.com>, Sam Ravnborg <sam@...nborg.org>, 
 Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, 
 Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, 
 David Airlie <airlied@...il.com>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Lee Jones <lee@...nel.org>, 
 Dmitry Torokhov <dmitry.torokhov@...il.com>, Pavel Machek <pavel@....cz>, 
 Liam Girdwood <lgirdwood@...il.com>, Mark Brown <broonie@...nel.org>, 
 Uwe Kleine-König <ukleinek@...nel.org>, 
 Krzysztof Kozlowski <krzk@...nel.org>, Chanwoo Choi <cw00.choi@...sung.com>, 
 Simona Vetter <simona@...ll.ch>, cros-qcom-dts-watchers@...omium.org, 
 Konrad Dybcio <konradybcio@...nel.org>, 
 Simona Vetter <simona.vetter@...ll.ch>, 
 Konrad Dybcio <konradybcio@...nel.org>
Cc: linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org, 
 linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, 
 dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org, 
 linux-input@...r.kernel.org, linux-leds@...r.kernel.org, 
 linux-pwm@...r.kernel.org, linux-samsung-soc@...r.kernel.org, 
 Dzmitry Sankouski <dsankouski@...il.com>
Subject: [PATCH v4 02/27] clk: qcom: clk-rcg2: name refactoring

clk-rcg2.c uses 2 variable names for pre divisor register value:
pre_div and hid_div.

Replace hid_div with pre_div. Update calc_rate docs to reflect, that
pre_div is not pure divisor, but a register value, and requires conversion.

Signed-off-by: Dzmitry Sankouski <dsankouski@...il.com>
---
 drivers/clk/qcom/clk-rcg2.c | 51 ++++++++++++++++++++++++++-------------------
 1 file changed, 29 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index bf26c5448f00..df491540ef39 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -153,13 +153,20 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
  *
  *          parent_rate     m
  *   rate = ----------- x  ---
- *            hid_div       n
+ *          pre_div_pure    n
+ *
+ * @param rate - Parent rate.
+ * @param m - Multiplier.
+ * @param n - Divisor.
+ * @param mode - Use zero to ignore m/n calculation.
+ * @param pre_div - Pre divisor register value. Pure pre divisor value
+ *                  related to pre_div as pre_div_pure = (pre_div + 1) / 2
  */
 static unsigned long
-calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
+calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div)
 {
-	if (hid_div)
-		rate = mult_frac(rate, 2, hid_div + 1);
+	if (pre_div)
+		rate = mult_frac(rate, 2, pre_div + 1);
 
 	if (mode)
 		rate = mult_frac(rate, m, n);
@@ -171,7 +178,7 @@ static unsigned long
 __clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, u32 cfg)
 {
 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-	u32 hid_div, m = 0, n = 0, mode = 0, mask;
+	u32 pre_div, m = 0, n = 0, mode = 0, mask;
 
 	if (rcg->mnd_width) {
 		mask = BIT(rcg->mnd_width) - 1;
@@ -186,10 +193,10 @@ __clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, u32 cfg)
 	}
 
 	mask = BIT(rcg->hid_width) - 1;
-	hid_div = cfg >> CFG_SRC_DIV_SHIFT;
-	hid_div &= mask;
+	pre_div = cfg >> CFG_SRC_DIV_SHIFT;
+	pre_div &= mask;
 
-	return calc_rate(parent_rate, m, n, mode, hid_div);
+	return calc_rate(parent_rate, m, n, mode, pre_div);
 }
 
 static unsigned long
@@ -715,7 +722,7 @@ static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
 	s64 src_rate = parent_rate;
 	s64 request;
 	u32 mask = BIT(rcg->hid_width) - 1;
-	u32 hid_div;
+	u32 pre_div;
 
 	if (src_rate == 810000000)
 		frac = frac_table_810m;
@@ -731,8 +738,8 @@ static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
 			continue;
 
 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
-				&hid_div);
-		f.pre_div = hid_div;
+				&pre_div);
+		f.pre_div = pre_div;
 		f.pre_div >>= CFG_SRC_DIV_SHIFT;
 		f.pre_div &= mask;
 		f.m = frac->num;
@@ -760,7 +767,7 @@ static int clk_edp_pixel_determine_rate(struct clk_hw *hw,
 	int delta = 100000;
 	s64 request;
 	u32 mask = BIT(rcg->hid_width) - 1;
-	u32 hid_div;
+	u32 pre_div;
 	int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
 
 	/* Force the correct parent */
@@ -781,13 +788,13 @@ static int clk_edp_pixel_determine_rate(struct clk_hw *hw,
 			continue;
 
 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
-				&hid_div);
-		hid_div >>= CFG_SRC_DIV_SHIFT;
-		hid_div &= mask;
+				&pre_div);
+		pre_div >>= CFG_SRC_DIV_SHIFT;
+		pre_div &= mask;
 
 		req->rate = calc_rate(req->best_parent_rate,
 				      frac->num, frac->den,
-				      !!frac->den, hid_div);
+				      !!frac->den, pre_div);
 		return 0;
 	}
 
@@ -974,7 +981,7 @@ static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned long request;
 	int delta = 100000;
 	u32 mask = BIT(rcg->hid_width) - 1;
-	u32 hid_div, cfg;
+	u32 pre_div, cfg;
 	int i, num_parents = clk_hw_get_num_parents(hw);
 
 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
@@ -995,8 +1002,8 @@ static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
 			continue;
 
 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
-				&hid_div);
-		f.pre_div = hid_div;
+				&pre_div);
+		f.pre_div = pre_div;
 		f.pre_div >>= CFG_SRC_DIV_SHIFT;
 		f.pre_div &= mask;
 		f.m = frac->num;
@@ -1564,7 +1571,7 @@ static int clk_rcg2_dp_set_rate(struct clk_hw *hw, unsigned long rate,
 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 	struct freq_tbl f = { 0 };
 	u32 mask = BIT(rcg->hid_width) - 1;
-	u32 hid_div, cfg;
+	u32 pre_div, cfg;
 	int i, num_parents = clk_hw_get_num_parents(hw);
 	unsigned long num, den;
 
@@ -1576,7 +1583,7 @@ static int clk_rcg2_dp_set_rate(struct clk_hw *hw, unsigned long rate,
 		return -EINVAL;
 
 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
-	hid_div = cfg;
+	pre_div = cfg;
 	cfg &= CFG_SRC_SEL_MASK;
 	cfg >>= CFG_SRC_SEL_SHIFT;
 
@@ -1587,7 +1594,7 @@ static int clk_rcg2_dp_set_rate(struct clk_hw *hw, unsigned long rate,
 		}
 	}
 
-	f.pre_div = hid_div;
+	f.pre_div = pre_div;
 	f.pre_div >>= CFG_SRC_DIV_SHIFT;
 	f.pre_div &= mask;
 

-- 
2.39.2


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ