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Message-ID: <ZuRppgocLShsfafm@kbusch-mbp>
Date: Fri, 13 Sep 2024 10:34:46 -0600
From: Keith Busch <kbusch@...nel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: Kai-Heng Feng <kai.heng.feng@...onical.com>,
	Nirmal Patel <nirmal.patel@...ux.intel.com>,
	jonathan.derrick@...ux.dev, acelan.kao@...onical.com,
	lpieralisi@...nel.org, kw@...ux.com, robh@...nel.org,
	bhelgaas@...gle.com, linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org, kaihengfeng@...il.com
Subject: Re: [PATCH] PCI: vmd: Delay interrupt handling on MTL VMD controller

On Fri, Sep 13, 2024 at 09:44:47PM +0530, Manivannan Sadhasivam wrote:
> 
> For the workaround, does it make sense to have a platform specific quirk in the
> NVMe driver? Because, reading the NVMe device register from VMD driver doesn't
> look plausible to me.

I don't know.

Does the breakage really need a register read on the device that
dispatched the original MSI? The VMD driver has no idea which device
sent it. If you really need to query every single device in the domain,
your performance is going to tank. It's bad enough issuing just a single
read in the IRQ handler, but to all of them?

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