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Message-ID: <fyoh72in62sfmsw3syqswr2p3pcv26zoce2tvlx53mu4lpoakx@ixyvy4oylms3>
Date: Fri, 13 Sep 2024 15:52:25 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Sricharan R <quic_srichara@...cinc.com>
Cc: andersson@...nel.org, konradybcio@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
ulf.hansson@...aro.org, linus.walleij@...aro.org, catalin.marinas@....com,
p.zabel@...gutronix.de, geert+renesas@...der.be, neil.armstrong@...aro.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, linux-mmc@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, quic_varada@...cinc.com
Subject: Re: [PATCH 7/8] arm64: dts: qcom: add IPQ5424 SoC and rdp466 board
support
On Fri, Sep 13, 2024 at 05:42:49PM GMT, Sricharan R wrote:
> From: Sricharan Ramabadhran <quic_srichara@...cinc.com>
>
> Add initial device tree support for the Qualcomm IPQ5424 SoC and
> rdp466 board.
>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 63 +++++
> arch/arm64/boot/dts/qcom/ipq5424.dtsi | 294 ++++++++++++++++++++
> 3 files changed, 358 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
> create mode 100644 arch/arm64/boot/dts/qcom/ipq5424.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 197ab325c0b9..46c4eb758799 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp474.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += ipq5424-rdp466.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
> new file mode 100644
> index 000000000000..c8597a9ba175
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
> @@ -0,0 +1,63 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * IPQ5018 MP03.1-C2 board device tree source
> + *
> + * Copyright (c) 2023 The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ipq5424.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ5424 RDP466";
> + compatible = "qcom,ipq5424-rdp466", "qcom,ipq5424";
> +
> + aliases {
> + serial0 = &uart1;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
Drop
> +};
> +
> +&tlmm {
> + sdc_default_state: sdc-default-state {
> + clk-pins {
> + pins = "gpio5";
> + function = "sdc_clk";
> + drive-strength = <8>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "gpio4";
> + function = "sdc_cmd";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "gpio0", "gpio1", "gpio2", "gpio3";
> + function = "sdc_data";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> + };
> +};
> +
> +&uart1 {
> + pinctrl-0 = <&uart1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&sleep_clk {
sleep comes between tlmm and uart1
> + clock-frequency = <32000>;
> +};
> +
> +&xo_board {
> + clock-frequency = <24000000>;
> +};
> +
> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> new file mode 100644
> index 000000000000..b6c08fac9482
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> @@ -0,0 +1,294 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * IPQ5424 device tree source
> + *
> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
> +#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&intc>;
> +
> + clocks {
> + xo_board: xo-board-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
I think Krzysztof lately suggested moving these clocks to board DT
files.
> + };
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
lowercase all labels
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
empty line (here and afterwards, before new subnodes.
> + L3_0: l3-cache {
> + compatible = "cache";
> + cache-level = <3>;
> + cache-unified;
> + };
> + };
> + };
> +
> + CPU1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x100>;
> + next-level-cache = <&L2_100>;
> + L2_100: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x200>;
> + next-level-cache = <&L2_200>;
> + L2_200: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x300>;
> + next-level-cache = <&L2_300>;
> + L2_300: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + };
> + };
> + };
> +
> + memory@...00000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0x0 0x80000000 0x0 0x0>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a55-pmu";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
I don't think you need CPU_MASK for GICv3 hosts.
> + };
> +
> + pmu-v7 {
> + compatible = "arm,cortex-a7-pmu";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + dsu-pmu {
> + compatible = "arm,dsu-pmu";
> + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
> + cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
> + status = "okay";
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + tz@...00000 {
> + reg = <0x0 0x8a600000 0x0 0x200000>;
> + no-map;
> + };
> + };
> +
> + soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0 0x10 0>;
> +
> + tlmm: pinctrl@...0000 {
> + compatible = "qcom,ipq5424-tlmm";
> + reg = <0 0x01000000 0 0x300000>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 50>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + uart1_pins: uart1-state {
> + pins = "gpio43", "gpio44";
> + function = "uart1";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> + };
> +
> + gcc: clock-controller@...0000 {
> + compatible = "qcom,ipq5424-gcc";
> + reg = <0 0x01800000 0 0x40000>;
> + clocks = <&xo_board>,
> + <&sleep_clk>,
> + <0>,
> + <0>,
> + <0>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #interconnect-cells = <1>;
> + };
> +
> + qupv3: geniqup@...0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0 0x01ac0000 0 0x2000>;
> + clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
> + <&gcc GCC_QUPV3_AHB_SLV_CLK>;
> + clock-names = "m-ahb", "s-ahb";
> + ranges;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + status = "okay";
> +
> + uart1: serial@...4000 {
> + compatible = "qcom,geni-debug-uart";
> + reg = <0 0x01a84000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_UART1_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
> + status = "okay";
> + };
> + };
> +
> + intc: interrupt-controller@...0000 {
> + compatible = "arm,gic-v3";
> + reg = <0 0xf200000 0 0x10000>, /* GICD */
> + <0 0xf240000 0 0x80000>; /* GICR * 4 regions */
> + #interrupt-cells = <0x3>;
> + interrupt-controller;
> + #redistributor-regions = <1>;
> + redistributor-stride = <0x0 0x20000>;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + mbi-ranges = <672 128>;
> + msi-controller;
No ITS?
> + };
> +
> + sdhc: mmc@...4000 {
> + compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>;
Please sort all nodes following the device addresses.
> + reg-names = "hc", "cqhci";
> +
> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&xo_board>;
> + clock-names = "iface", "core", "xo";
> +
> + status = "disabled";
> + };
> +
> + timer@...0000 {
> + compatible = "arm,armv7-timer-mem";
> + reg = <0 0xf420000 0 0x1000>;
> + ranges = <0 0 0 0x10000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + frame@...1000 {
> + reg = <0xf421000 0x1000>,
> + <0xf422000 0x1000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <0>;
> + };
> +
> + frame@...3000 {
> + reg = <0xf423000 0x1000>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <1>;
> + status = "disabled";
> + };
> +
> + frame@...5000 {
> + reg = <0xf425000 0x1000>,
> + <0xf426000 0x1000>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <2>;
> + status = "disabled";
> + };
> +
> + frame@...7000 {
> + reg = <0xf427000 0x1000>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <3>;
> + status = "disabled";
> + };
> +
> + frame@...9000 {
> + reg = <0xf429000 0x1000>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <4>;
> + status = "disabled";
> + };
> +
> + frame@...b000 {
> + reg = <0xf42b000 0x1000>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <5>;
> + status = "disabled";
> + };
> +
> + frame@...d000 {
> + reg = <0xf42d000 0x1000>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <6>;
> + status = "disabled";
> + };
> + };
> +
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +};
> --
> 2.34.1
>
--
With best wishes
Dmitry
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