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Message-ID: <20240914052413.68177-25-towinchenmi@gmail.com>
Date: Sat, 14 Sep 2024 13:17:30 +0800
From: Nick Chan <towinchenmi@...il.com>
To: Hector Martin <marcan@...can.st>,
Sven Peter <sven@...npeter.dev>,
Alyssa Rosenzweig <alyssa@...enzweig.io>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
"Rafael J . Wysocki" <rafael@...nel.org>,
Viresh Kumar <viresh.kumar@...aro.org>,
Linus Walleij <linus.walleij@...aro.org>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Guenter Roeck <linux@...ck-us.net>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Mark Kettenis <kettenis@...nbsd.org>,
asahi@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org,
linux-gpio@...r.kernel.org,
linux-watchdog@...r.kernel.org
Cc: Nick Chan <towinchenmi@...il.com>,
Ivaylo Ivanov <ivo.ivanov.ivanov1@...il.com>,
Konrad Dybcio <konradybcio@...nel.org>
Subject: [PATCH v2 21/22] arm64: dts: apple: t8010: Add cpufreq nodes
Add cpufreq nodes for the A10 SoC.
The Apple iPod touch 7 can only go up to 1.64 GHz, so the higher operating
points are in t8010-fast.dtsi.
A10 consists of logical cores that switches between E-mode and P-mode
depending on the current p-state. Each mode have different capacities so
the E-mode frequencies are adjusted to make performance scale linearly
with clock speed.
Signed-off-by: Nick Chan <towinchenmi@...il.com>
---
arch/arm64/boot/dts/apple/t8010-fast.dtsi | 22 ++++++++
arch/arm64/boot/dts/apple/t8010.dtsi | 67 +++++++++++++++++++++++
2 files changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t8010-fast.dtsi b/arch/arm64/boot/dts/apple/t8010-fast.dtsi
index 4bdf1c3eccfe..b5a2c78ca9e9 100644
--- a/arch/arm64/boot/dts/apple/t8010-fast.dtsi
+++ b/arch/arm64/boot/dts/apple/t8010-fast.dtsi
@@ -6,3 +6,25 @@
*/
#include "t8010.dtsi"
+
+/ {
+ opp: opp-table {
+ opp08 {
+ opp-hz = /bits/ 64 <1944000000>;
+ opp-level = <8>;
+ opp-microvolt = <816000>;
+ };
+
+ opp09 {
+ opp-hz = /bits/ 64 <2244000000>;
+ opp-level = <9>;
+ opp-microvolt = <922000>;
+ };
+
+ opp10 {
+ opp-hz = /bits/ 64 <2340000000>;
+ opp-level = <10>;
+ opp-microvolt = <922000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/apple/t8010.dtsi
index 926a0f501477..e27d2b5e3df1 100644
--- a/arch/arm64/boot/dts/apple/t8010.dtsi
+++ b/arch/arm64/boot/dts/apple/t8010.dtsi
@@ -50,6 +50,8 @@ cpu0: cpu@0 {
compatible = "apple,hurricane-zephyr";
reg = <0x0 0x0>;
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&opp>;
+ performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
};
@@ -58,11 +60,70 @@ cpu1: cpu@1 {
compatible = "apple,hurricane-zephyr";
reg = <0x0 0x1>;
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&opp>;
+ performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
};
};
+ opp: opp-table {
+ compatible = "operating-points-v2";
+
+ /*
+ * The E-core frequencies are adjusted so performance scales
+ * linearly with reported clock speed.
+ */
+
+ opp01 {
+ opp-hz = /bits/ 64 <149000000>; /* 396 MHz, E-core */
+ opp-level = <1>;
+ opp-microvolt = <525000>;
+ };
+
+ opp02 {
+ opp-hz = /bits/ 64 <275000000>; /* 732 MHz, E-core */
+ opp-level = <2>;
+ opp-microvolt = <541000>;
+ };
+
+ opp03 {
+ opp-hz = /bits/ 64 <410000000>; /* 1092 MHz, E-core */
+ opp-level = <3>;
+ opp-microvolt = <603000>;
+ };
+
+ /* The following operating points are handled by the P-cores */
+ opp04 {
+ opp-hz = /bits/ 64 <756000000>;
+ opp-level = <4>;
+ opp-microvolt = <559000>;
+ };
+
+ opp05 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-level = <5>;
+ opp-microvolt = <609000>;
+ };
+
+ opp06 {
+ opp-hz = /bits/ 64 <1356000000>;
+ opp-level = <6>;
+ opp-microvolt = <650000>;
+ };
+
+ opp07 {
+ opp-hz = /bits/ 64 <1644000000>;
+ opp-level = <7>;
+ opp-microvolt = <725000>;
+ };
+
+ /*
+ * The iPod touch 7 supports up to 1.6 GHz, faster operating
+ * points for other devices are in t8010-fast.dtsi
+ */
+ };
+
memory@...000000 {
device_type = "memory";
reg = <0x8 0 0 0>; /* To be filled by loader */
@@ -86,6 +147,12 @@ soc {
nonposted-mmio;
ranges;
+ cpufreq: performance-controller@...f20000 {
+ compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+ reg = <0x2 0x2f20000 0 0x1000>;
+ #performance-domain-cells = <0>;
+ };
+
serial0: serial@...0c0000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x0a0c0000 0x0 0x4000>;
--
2.46.0
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