linux-kernel - [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3

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Message-ID: <7ede7ca6-f8db-4b38-a1cc-8be3d0db7fae@gmail.com>
Date: Sun, 15 Sep 2024 10:45:51 -0400
From: Jesse Taube <mr.bossman075@...il.com>
To: Yixun Lan <dlan@...too.org>
Cc: Yangyu Chen <cyy@...self.name>, Jisheng Zhang <jszhang@...nel.org>,
 Inochi Amaoto <inochiama@...look.com>, Icenowy Zheng <uwu@...nowy.me>,
 Meng Zhang <zhangmeng.kevin@...cemit.com>, Meng Zhang
 <kevin.z.m@...mail.com>, devicetree@...r.kernel.org,
 linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
 linux-gpio@...r.kernel.org, Yixun Lan <dlan@...too.org>,
 Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>,
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
 Conor Dooley <conor@...nel.org>
Subject: [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in
 BPI-F3


Before pinctrl driver implemented, the uart0 controller reply on
bootloader for setting correct pin mux and configurations.

Now, let's add pinctrl property to uart0 of Bananapi-F3 board.

Signed-off-by: Yixun Lan <dlan@...too.org>
---
  arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts |  3 +++
  arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi    | 20 ++++++++++++++++++++
  arch/riscv/boot/dts/spacemit/k1.dtsi            |  5 +++++
  3 files changed, 28 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts 
b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 023274189b492..bc88d4de25a62 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -4,6 +4,7 @@
   */

  #include "k1.dtsi"
+#include "k1-pinctrl.dtsi"

  / {
  	model = "Banana Pi BPI-F3";
@@ -15,5 +16,7 @@ chosen {
  };

  &uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_2_cfg>;
  	status = "okay";
  };
diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi 
b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
new file mode 100644
index 0000000000000..a8eac5517f857
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024 Yixun Lan <dlan@...too.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define K1_PADCONF(pin, func) (((pin) << 16) | (func))

It would be nice to have a pinfunc header like
arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h.
It would reference and encode the data of "3.2 Pin Multiplex" in
https://developer.spacemit.com/documentation?token=An1vwTwKaigaXRkYfwmcznTXned 
, the document you attached in the summary.

Otherwise,
Acked-by: Jesse Taube <Mr.Bossman075@...il.com>

+
+&pinctrl {
+	uart0_2_cfg: uart0-2-cfg {
+		uart0-2-pins {
+			pinmux = <K1_PADCONF(68, 2)>,
+				 <K1_PADCONF(69, 2)>;
+
+			bias-pull-up = <0>;
+			drive-strength = <32>;
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi 
b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 0777bf9e01183..a2d5f7d4a942a 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -416,6 +416,11 @@ uart9: serial@...17800 {
  			status = "disabled";
  		};

+		pinctrl: pinctrl@...1e000 {
+			compatible = "spacemit,k1-pinctrl";
+			reg = <0x0 0xd401e000 0x0 0x400>;
+		};
+
  		plic: interrupt-controller@...00000 {
  			compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
  			reg = <0x0 0xe0000000 0x0 0x4000000>;

-- 
2.45.2