linux-kernel - Re: [PATCH v2 3/5] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3

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Message-ID: <c4696a9d-e3f2-4ff5-8323-84f75f2f1a68@kernel.org>
Date: Tue, 17 Sep 2024 01:29:58 +0200
From: Konrad Dybcio <konradybcio@...nel.org>
To: Qiang Yu <quic_qianyu@...cinc.com>, manivannan.sadhasivam@...aro.org,
 vkoul@...nel.org, kishon@...nel.org, robh@...nel.org, andersson@...nel.org,
 konradybcio@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
 mturquette@...libre.com, sboyd@...nel.org, abel.vesa@...aro.org,
 quic_msarkar@...cinc.com, quic_devipriy@...cinc.com
Cc: dmitry.baryshkov@...aro.org, kw@...ux.com, lpieralisi@...nel.org,
 neil.armstrong@...aro.org, linux-arm-msm@...r.kernel.org,
 linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
 linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
 linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 3/5] phy: qcom: qmp: Add phy register and clk setting
 for x1e80100 PCIe3

On 13.09.2024 10:37 AM, Qiang Yu wrote:
> Currently driver supports only x4 lane based functionality using tx/rx and
> tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3,
> PCIe3 related QMP PHY provides additional programming which are available
> as txz and rxz based register set. Hence adds txz and rxz based registers
> usage and programming sequences. Phy register setting for txz and rxz will
> be applied to all 8 lanes. Some lanes may have different settings on
> several registers than txz/rxz, these registers should be programmed after
> txz/rxz programming sequences completing.
> 
> Besides, x1e80100 SoC uses QMP phy with version v6.30 for PCIe Gen4 x8.
> Add the new register offsets in a dedicated header file.
> 
> Signed-off-by: Qiang Yu <quic_qianyu@...cinc.com>
> ---

Reviewed-by: Konrad Dybcio <konradybcio@...nel.org>

Konrad