linux-kernel - Re: [PATCH 05/21] clock:Add driver for ADI ADSP-SC5xx PLL

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Message-ID: <768d8629-8020-4b9e-8246-2045f224830b@kernel.org>
Date: Mon, 16 Sep 2024 08:46:22 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: arturs.artamonovs@...log.com, Catalin Marinas <catalin.marinas@....com>,
 Will Deacon <will@...nel.org>, Greg Malysa <greg.malysa@...esys.com>,
 Philipp Zabel <p.zabel@...gutronix.de>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Utsav Agarwal <Utsav.Agarwal@...log.com>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Linus Walleij <linus.walleij@...aro.org>,
 Bartosz Golaszewski <brgl@...ev.pl>, Thomas Gleixner <tglx@...utronix.de>,
 Andi Shyti <andi.shyti@...nel.org>,
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
 Jiri Slaby <jirislaby@...nel.org>, Arnd Bergmann <arnd@...db.de>,
 Olof Johansson <olof@...om.net>, soc@...nel.org
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
 devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
 linux-gpio@...r.kernel.org, linux-i2c@...r.kernel.org,
 linux-serial@...r.kernel.org, adsp-linux@...log.com,
 Nathan Barrett-Morrison <nathan.morrison@...esys.com>
Subject: Re: [PATCH 05/21] clock:Add driver for ADI ADSP-SC5xx PLL

On 12/09/2024 20:24, Arturs Artamonovs via B4 Relay wrote:
> From: Arturs Artamonovs <arturs.artamonovs@...log.com>
> 
> Implements clock tree, no dynamic pll rate change.
> 
> Signed-off-by: Arturs Artamonovs <Arturs.Artamonovs@...log.com>
> Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@...esys.com>
> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@...esys.com>
> Co-developed-by: Greg Malysa <greg.malysa@...esys.com>
> Signed-off-by: Greg Malysa <greg.malysa@...esys.com>
> ---
>  drivers/clk/adi/clk-adi-pll.c | 151 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/adi/clk.h         |  99 +++++++++++++++++++++++++++
>  2 files changed, 250 insertions(+)


How do you even build this code? Never built, so never tested?

> +struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name,
> +	void __iomem *base, u8 shift, u8 width, u32 m_offset,
> +		spinlock_t *lock)
> +{
> +	struct clk_sc5xx_cgu_pll *pll;
> +	struct clk *clk;
> +	struct clk_init_data init;
> +
> +	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> +	if (!pll)
> +		return ERR_PTR(-ENOMEM);
> +
> +	init.name = name;
> +	init.flags = CLK_SET_RATE_PARENT;
> +	init.parent_names = &parent_name;
> +	init.num_parents = 1;
> +	init.ops = &clk_sc5xx_cgu_pll_ops;
> +
> +	pll->base = base;
> +	pll->hw.init = &init;
> +	pll->lock = lock;
> +	pll->shift = shift;
> +	pll->mask = GENMASK(width-1, 0) << shift;
> +	pll->msel = pll->mask + 1;
> +	pll->m_offset = m_offset;
> +
> +	clk = clk_register(NULL, &pll->hw);
> +	if (IS_ERR(clk)) {
> +		pr_err("%s: Failed to register, code %lu\n", __func__,
> +			PTR_ERR(clk));
> +	}
> +
> +	return clk;
> +}
> +
> +MODULE_DESCRIPTION("Analog Devices CLock PLL driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Greg Malysa <greg.malysa@...esys.com>");
> +

Multiple patches have messy blank line handling...

> diff --git a/drivers/clk/adi/clk.h b/drivers/clk/adi/clk.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..e17aa719c2170149a6a1a60dd4390a29f06e7296
> --- /dev/null
> +++ b/drivers/clk/adi/clk.h


Best regards,
Krzysztof