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Message-ID: <247345579659D8F7+20240916034603.59120-1-wangyuli@uniontech.com>
Date: Mon, 16 Sep 2024 11:46:02 +0800
From: WangYuli <wangyuli@...ontech.com>
To: stable@...r.kernel.org,
gregkh@...uxfoundation.org,
sashal@...nel.org,
william.qiu@...rfivetech.com,
emil.renner.berthing@...onical.com,
conor.dooley@...rochip.com,
wangyuli@...ontech.com
Cc: kernel@...il.dk,
conor@...nel.org,
robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu,
linux-riscv@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 6.6 v3] riscv: dts: starfive: add assigned-clock* to limit frquency
From: William Qiu <william.qiu@...rfivetech.com>
[ Upstream commit af571133f7ae028ec9b5fdab78f483af13bf28d3 ]
In JH7110 SoC, we need to go by-pass mode, so we need add the
assigned-clock* properties to limit clock frquency.
Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@...onical.com>
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: WangYuli <wangyuli@...ontech.com>
---
.../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 062b97c6e7df..4874e3bb42ab 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -204,6 +204,8 @@ &i2c6 {
&mmc0 {
max-frequency = <100000000>;
+ assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+ assigned-clock-rates = <50000000>;
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
@@ -220,6 +222,8 @@ &mmc0 {
&mmc1 {
max-frequency = <100000000>;
+ assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
+ assigned-clock-rates = <50000000>;
bus-width = <4>;
no-sdio;
no-mmc;
--
2.43.0
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