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Message-ID: <hyhcycqedztrstcl2aixs6e2xwiowlrijkj3g6a2kheqap34qq@hhqxp5i3mbyq>
Date: Mon, 16 Sep 2024 17:20:06 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Qiang Yu <quic_qianyu@...cinc.com>
Cc: manivannan.sadhasivam@...aro.org, vkoul@...nel.org, kishon@...nel.org,
robh@...nel.org, andersson@...nel.org, konradybcio@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, mturquette@...libre.com, sboyd@...nel.org, abel.vesa@...aro.org,
quic_msarkar@...cinc.com, quic_devipriy@...cinc.com, dmitry.baryshkov@...aro.org,
kw@...ux.com, lpieralisi@...nel.org, neil.armstrong@...aro.org,
linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 2/5] dt-bindings: PCI: qcom: Add OPP table for X1E80100
On Fri, Sep 13, 2024 at 01:37:21AM -0700, Qiang Yu wrote:
> Add OPP table so that PCIe is able to adjust power domain performance
> state and ICC peak bw according to PCIe gen speed and link width.
>
> Signed-off-by: Qiang Yu <quic_qianyu@...cinc.com>
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzk@...nel.org>
Best regards,
Krzysztof
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