Message-ID: <ZujGqOVbYZ8+8XPu@debug.ba.rivosinc.com>
Date: Mon, 16 Sep 2024 17:00:40 -0700
From: Deepak Gupta <debug@...osinc.com>
To: Andy Chiu <andybnac@...il.com>
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Subject: Re: [PATCH v4 21/30] riscv/traps: Introduce software check exception

On Fri, Sep 13, 2024 at 09:35:50PM +0200, Andy Chiu wrote:
>Hi Deepak
>
>Deepak Gupta <debug@...osinc.com> 於 2024年9月13日 週五 上午2:32寫道：
>>
>> zicfiss / zicfilp introduces a new exception to priv isa `software check
>> exception` with cause code = 18. This patch implements software check
>> exception.
>>
>> Additionally it implements a cfi violation handler which checks for code
>> in xtval. If xtval=2, it means that sw check exception happened because of
>> an indirect branch not landing on 4 byte aligned PC or not landing on
>> `lpad` instruction or label value embedded in `lpad` not matching label
>> value setup in `x7`. If xtval=3, it means that sw check exception happened
>> because of mismatch between link register (x1 or x5) and top of shadow
>> stack (on execution of `sspopchk`).
>>
>> In case of cfi violation, SIGSEGV is raised with code=SEGV_CPERR.
>> SEGV_CPERR was introduced by x86 shadow stack patches.
>>
>> Signed-off-by: Deepak Gupta <debug@...osinc.com>
>> ---
>>  arch/riscv/include/asm/asm-prototypes.h |  1 +
>>  arch/riscv/include/asm/entry-common.h   |  2 ++
>>  arch/riscv/kernel/entry.S               |  3 ++
>>  arch/riscv/kernel/traps.c               | 38 +++++++++++++++++++++++++
>>  4 files changed, 44 insertions(+)
>>
>> diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/asm/asm-prototypes.h
>> index cd627ec289f1..5a27cefd7805 100644
>> --- a/arch/riscv/include/asm/asm-prototypes.h
>> +++ b/arch/riscv/include/asm/asm-prototypes.h
>> @@ -51,6 +51,7 @@ DECLARE_DO_ERROR_INFO(do_trap_ecall_u);
>>  DECLARE_DO_ERROR_INFO(do_trap_ecall_s);
>>  DECLARE_DO_ERROR_INFO(do_trap_ecall_m);
>>  DECLARE_DO_ERROR_INFO(do_trap_break);
>> +DECLARE_DO_ERROR_INFO(do_trap_software_check);
>>
>>  asmlinkage void handle_bad_stack(struct pt_regs *regs);
>>  asmlinkage void do_page_fault(struct pt_regs *regs);
>> diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h
>> index 2293e535f865..4068c7e5452a 100644
>> --- a/arch/riscv/include/asm/entry-common.h
>> +++ b/arch/riscv/include/asm/entry-common.h
>> @@ -39,4 +39,6 @@ static inline int handle_misaligned_store(struct pt_regs *regs)
>>  }
>>  #endif
>>
>> +bool handle_user_cfi_violation(struct pt_regs *regs);
>> +
>>  #endif /* _ASM_RISCV_ENTRY_COMMON_H */
>> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
>> index ca9203e6d76d..2ec75ba864a8 100644
>> --- a/arch/riscv/kernel/entry.S
>> +++ b/arch/riscv/kernel/entry.S
>> @@ -384,6 +384,9 @@ SYM_DATA_START_LOCAL(excp_vect_table)
>>         RISCV_PTR do_page_fault   /* load page fault */
>>         RISCV_PTR do_trap_unknown
>>         RISCV_PTR do_page_fault   /* store page fault */
>> +       RISCV_PTR do_trap_unknown /* cause=16 */
>> +       RISCV_PTR do_trap_unknown /* cause=17 */
>> +       RISCV_PTR do_trap_software_check /* cause=18 is sw check exception */
>>  SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end)
>>
>>  #ifndef CONFIG_MMU
>> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
>> index 51ebfd23e007..32d1453bed72 100644
>> --- a/arch/riscv/kernel/traps.c
>> +++ b/arch/riscv/kernel/traps.c
>> @@ -354,6 +354,44 @@ void do_trap_ecall_u(struct pt_regs *regs)
>>
>>  }
>>
>> +#define CFI_TVAL_FCFI_CODE     2
>> +#define CFI_TVAL_BCFI_CODE     3
>> +/* handle cfi violations */
>> +bool handle_user_cfi_violation(struct pt_regs *regs)
>> +{
>> +       bool ret = false;
>> +       unsigned long tval = csr_read(CSR_TVAL);
>> +
>> +       if (((tval == CFI_TVAL_FCFI_CODE) && cpu_supports_indirect_br_lp_instr()) ||
>> +               ((tval == CFI_TVAL_BCFI_CODE) && cpu_supports_shadow_stack())) {
>> +               do_trap_error(regs, SIGSEGV, SEGV_CPERR, regs->epc,
>> +                                         "Oops - control flow violation");
>> +               ret = true;
>> +       }
>> +
>> +       return ret;
>> +}
>> +/*
>> + * software check exception is defined with risc-v cfi spec. Software check
>> + * exception is raised when:-
>> + * a) An indirect branch doesn't land on 4 byte aligned PC or `lpad`
>> + *    instruction or `label` value programmed in `lpad` instr doesn't
>> + *    match with value setup in `x7`. reported code in `xtval` is 2.
>> + * b) `sspopchk` instruction finds a mismatch between top of shadow stack (ssp)
>> + *    and x1/x5. reported code in `xtval` is 3.
>> + */
>
>It seems like this trap handler does not follow generic entry. This
>can cause problems as signal delivery is done in
>irqentry_exit_to_user_mode(). Please reference the commit f0bddf50586d
>("riscv: entry: Convert to generic entry") for more information.

Ack. will fix it.

>
>> +asmlinkage __visible __trap_section void do_trap_software_check(struct pt_regs *regs)
>> +{
>> +       if (user_mode(regs)) {
>> +               /* not a cfi violation, then merge into flow of unknown trap handler */
>> +               if (!handle_user_cfi_violation(regs))
>> +                       do_trap_unknown(regs);
>> +       } else {
>> +               /* sw check exception coming from kernel is a bug in kernel */
>> +               die(regs, "Kernel BUG");
>> +       }
>> +}
>> +
>>  #ifdef CONFIG_MMU
>>  asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs)
>>  {
>> --
>> 2.45.0
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@...ts.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>Cheers,
>Andy

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