linux-kernel - Re: [PATCH v3] drm/i915/cx0: Set power state to ready only on owned PHY lanes

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Message-ID: <172660167214.57276.12139169672475915963@gjsousa-mobl2>
Date: Tue, 17 Sep 2024 16:34:32 -0300
From: Gustavo Sousa <gustavo.sousa@...el.com>
To: Vamsi Krishna Brahmajosyula <vamsikrishna.brahmajosyula@...il.com>,
	<airlied@...il.com>, <daniel@...ll.ch>, <jani.nikula@...ux.intel.com>,
	<joonas.lahtinen@...ux.intel.com>, <rodrigo.vivi@...el.com>,
	<tursulin@...ulin.net>
CC: <skhan@...uxfoundation.org>, <intel-gfx@...ts.freedesktop.org>,
	<intel-xe@...ts.freedesktop.org>, <dri-devel@...ts.freedesktop.org>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3] drm/i915/cx0: Set power state to ready only on owned PHY lanes

Quoting Vamsi Krishna Brahmajosyula (2024-09-17 09:44:49-03:00)
>In DP alt mode, when pin assignment is D, only one PHY lane is owned
>by the display. intel_cx0pll_enable currently performs a power state
>ready on both the lanes in all cases.
>
>Address the todo to perfom power state ready on owned lanes.
>
>Tested on Meteor Lake-P [Intel Arc Graphics] with DP alt mode.
>
>v2 -> v3:
>- Fix changelog per Jani Nikula's feedback
>v1 -> v2: Address Gustavo Sousa's feedback
>- Use owned lanes mask to set Phy power state to Ready, instead of
>  maxpclk_lane with DP alt mode check.
>- Owned lanes are obtained from intel_cx0_get_owned_lane_mask().
>
>Signed-off-by: Vamsi Krishna Brahmajosyula <vamsikrishna.brahmajosyula@...il.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@...el.com>

For some reason this is not showing up on Patchwork[1].

[1]: https://patchwork.freedesktop.org/project/intel-gfx/series/

--
Gustavo Sousa

>---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index 4a6c3040ca15..cbed53d3b250 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -2934,6 +2934,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>         enum phy phy = intel_encoder_to_phy(encoder);
>         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>         bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
>+        u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
>         u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
>                                           INTEL_CX0_LANE0;
>         intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
>@@ -2948,10 +2949,9 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>         intel_cx0_phy_lane_reset(encoder, lane_reversal);
> 
>         /*
>-         * 3. Change Phy power state to Ready.
>-         * TODO: For DP alt mode use only one lane.
>+         * 3. Change Phy power state to Ready on owned lanes.
>          */
>-        intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
>+        intel_cx0_powerdown_change_sequence(encoder, owned_lane_mask,
>                                             CX0_P2_STATE_READY);
> 
>         /*
>
>base-commit: ad060dbbcfcfcba624ef1a75e1d71365a98b86d8
>-- 
>2.46.0
>