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Message-ID: <CACu1E7FGMX8KTbhS1HAEumD9Dx7K334bnJecg14-mSQBaZ4V5g@mail.gmail.com>
Date: Wed, 18 Sep 2024 18:51:50 +0100
From: Connor Abbott <cwabbott0@...il.com>
To: Akhil P Oommen <quic_akhilpo@...cinc.com>
Cc: Rob Clark <robdclark@...il.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konrad.dybcio@...aro.org>, Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Marijn Suijten <marijn.suijten@...ainline.org>, David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Puranam V G Tejaswi <quic_pvgtejas@...cinc.com>
Subject: Re: [PATCH 1/3] drm/msm/a6xx: Add support for A663
On Tue, Sep 17, 2024 at 9:39 PM Akhil P Oommen <quic_akhilpo@...cinc.com> wrote:
>
> From: Puranam V G Tejaswi <quic_pvgtejas@...cinc.com>
>
> Add support for Adreno 663 found on sa8775p based platforms.
>
> Signed-off-by: Puranam V G Tejaswi <quic_pvgtejas@...cinc.com>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@...cinc.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 19 ++++++++++++++++++
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++++++-
> drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 33 +++++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++
> 4 files changed, 64 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 0312b6ee0356..8d8d0d7630f0 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -972,6 +972,25 @@ static const struct adreno_info a6xx_gpus[] = {
> .prim_fifo_threshold = 0x00300200,
> },
> .address_space_size = SZ_16G,
> + }, {
> + .chip_ids = ADRENO_CHIP_IDS(0x06060300),
> + .family = ADRENO_6XX_GEN4,
> + .fw = {
> + [ADRENO_FW_SQE] = "a660_sqe.fw",
> + [ADRENO_FW_GMU] = "a663_gmu.bin",
> + },
> + .gmem = SZ_1M + SZ_512K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> + ADRENO_QUIRK_HAS_HW_APRIV,
> + .init = a6xx_gpu_init,
> + .a6xx = &(const struct a6xx_info) {
> + .hwcg = a690_hwcg,
> + .protect = &a660_protect,
> + .gmu_cgc_mode = 0x00020200,
> + .prim_fifo_threshold = 0x00300200,
> + },
> + .address_space_size = SZ_16G,
> }, {
> .chip_ids = ADRENO_CHIP_IDS(0x06030500),
> .family = ADRENO_6XX_GEN4,
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 06cab2c6fd66..e317780caeae 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -541,6 +541,12 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> gpu->ubwc_config.macrotile_mode = 1;
> }
>
> + if (adreno_is_a663(gpu)) {
> + gpu->ubwc_config.highest_bank_bit = 13;
> + gpu->ubwc_config.ubwc_swizzle = 0x4;
It's already been mentioned in the Mesa MR, but since this is the
first GPU with level2_swizzling_dis set, the relevant vulkan CTS tests
need to be tested with
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26578
rebased on your Mesa enablement patch.
> + gpu->ubwc_config.macrotile_mode = 1;
> + }
> +
> if (adreno_is_7c3(gpu)) {
> gpu->ubwc_config.highest_bank_bit = 14;
> gpu->ubwc_config.amsbc = 1;
> @@ -1062,7 +1068,7 @@ static int hw_init(struct msm_gpu *gpu)
> if (adreno_is_a690(adreno_gpu))
> gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90);
> /* Set dualQ + disable afull for A660 GPU */
> - else if (adreno_is_a660(adreno_gpu))
> + else if (adreno_is_a660(adreno_gpu) || adreno_is_a663(adreno_gpu))
> gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906);
> else if (adreno_is_a7xx(adreno_gpu))
> gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG,
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> index cdb3f6e74d3e..f1196d66055c 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> @@ -478,6 +478,37 @@ static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> msg->cnoc_cmds_data[1][0] = 0x60000001;
> }
>
> +static void a663_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> +{
> + /*
> + * Send a single "off" entry just to get things running
> + * TODO: bus scaling
> + */
> + msg->bw_level_num = 1;
> +
> + msg->ddr_cmds_num = 3;
> + msg->ddr_wait_bitmask = 0x07;
> +
> + msg->ddr_cmds_addrs[0] = 0x50004;
> + msg->ddr_cmds_addrs[1] = 0x50000;
> + msg->ddr_cmds_addrs[2] = 0x500b4;
> +
> + msg->ddr_cmds_data[0][0] = 0x40000000;
> + msg->ddr_cmds_data[0][1] = 0x40000000;
> + msg->ddr_cmds_data[0][2] = 0x40000000;
> +
> + /*
> + * These are the CX (CNOC) votes - these are used by the GMU but the
> + * votes are known and fixed for the target
> + */
> + msg->cnoc_cmds_num = 1;
> + msg->cnoc_wait_bitmask = 0x01;
> +
> + msg->cnoc_cmds_addrs[0] = 0x50058;
> + msg->cnoc_cmds_data[0][0] = 0x40000000;
> + msg->cnoc_cmds_data[1][0] = 0x60000001;
> +}
> +
> static void adreno_7c3_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> {
> /*
> @@ -646,6 +677,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
> adreno_7c3_build_bw_table(&msg);
> else if (adreno_is_a660(adreno_gpu))
> a660_build_bw_table(&msg);
> + else if (adreno_is_a663(adreno_gpu))
> + a663_build_bw_table(&msg);
> else if (adreno_is_a690(adreno_gpu))
> a690_build_bw_table(&msg);
> else if (adreno_is_a730(adreno_gpu))
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 58d7e7915c57..10f8f25d8826 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -455,6 +455,11 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
> return adreno_is_revn(gpu, 680);
> }
>
> +static inline int adreno_is_a663(const struct adreno_gpu *gpu)
> +{
> + return gpu->info->chip_ids[0] == 0x06060300;
> +}
> +
> static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> {
> return gpu->info->chip_ids[0] == 0x06090000;
>
> --
> 2.45.2
>
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